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    Semiconductor memory devices and memory systems
    11.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11860734B2

    公开(公告)日：2024-01-02

    申请号：US17736154

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

    IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/07

    CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048 ,  H03M13/1108

    Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    12.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11829614B2

    公开(公告)日：2023-11-28

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    14.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230037996A1

    公开(公告)日：2023-02-09

    申请号：US17718422

    申请日：2022-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho

    IPC: H03M13/11 ,  H03M13/15 ,  G11C15/04 ,  G11C17/16

    Abstract: An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    16.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240233798A9

    公开(公告)日：2024-07-11

    申请号：US18327335

    申请日：2023-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    18.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240135980A1

    公开(公告)日：2024-04-25

    申请号：US18327335

    申请日：2023-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

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