公开(公告)号：USD1040796S1

公开(公告)日：2024-09-03

申请号：US29888231

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Designer： Nam-Kyu Kim ,  Bum-Soo Park ,  Seung-Ho Jang

Abstract: FIG. 1 is a top front perspective view of a case for electronic device showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left side view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof;
FIG. 8 is a bottom rear perspective view thereof;
FIG. 9 is an enlarged view of the delineated portion 9 in FIG. 1; and,
FIG. 10 is an enlarged view of the delineated portion 10 in FIG. 8.
The dashed broken lines in the figures depict portions of the case for electronic device that form no part of the claimed design.
The dot-dash broken lines in the figures delineating portions of the claimed design that are illustrated in enlargements form no part of the claimed design.

公开(公告)号：US10727348B2

公开(公告)日：2020-07-28

申请号：US16367813

申请日：2019-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US10388791B2

公开(公告)日：2019-08-20

申请号：US15398788

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US20190214498A1

公开(公告)日：2019-07-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10079305B2

公开(公告)日：2018-09-18

申请号：US14861748

申请日：2015-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongchan Lee ,  Nam-Kyu Kim ,  JinBum Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/76 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

公开(公告)号：US20150031183A1

公开(公告)日：2015-01-29

申请号：US14485035

申请日：2014-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Abstract translation: 通过在包括硅和锗或锗的外延区域上生长硅来制造具有硅化物源极/漏极区的半导体器件。 在该方法中，在半导体衬底上形成有栅极绝缘层的栅电极。 在栅极两侧的半导体衬底中形成外延层。 形成硅层来覆盖外延层。 硅层和金属材料反应形成硅化物层。 在PMOS中，外延层具有暴露在有源区的上表面上方的顶表面和倾斜侧表面。 硅层在外延层上生长，以覆盖顶部和倾斜表面。

公开(公告)号：US10170622B2

公开(公告)日：2019-01-01

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20170278967A1

公开(公告)日：2017-09-28

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20160133748A1

公开(公告)日：2016-05-12

申请号：US14995215

申请日：2016-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20160027902A1

公开(公告)日：2016-01-28

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/04 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。