公开(公告)号：US12279537B2

公开(公告)日：2025-04-15

申请号：US17468739

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Yoon ,  O Ik Kwon ,  Yun Seung Kang ,  Sang-Kuk Kim ,  Gwang-Hyun Baek ,  Tae Hyung Lee ,  Su Jin Jeon

IPC: H10N70/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

公开(公告)号：US11723221B2

公开(公告)日：2023-08-08

申请号：US17113609

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kuk Kim ,  Yunseung Kang ,  Oik Kwon ,  Yeonji Kim ,  Sujin Jeon

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10N70/063

Abstract: A three-dimensional (3D) semiconductor memory device including first cell stacks arranged in first and second directions; second cell stacks disposed on the first cell stacks and arranged in the first and second directions; first conductive lines extending in the first direction and provided between a substrate and the first cell stacks; common conductive lines extending in the second direction and provided between the first and second cell stacks; etch stop patterns extending in the second direction and provided between the common conductive lines and top surfaces of the first cell stacks; second conductive lines extending in the first direction and provided on the second cell stacks; and a capping pattern covering a sidewall of the common conductive lines and a sidewall of the etch stop patterns, wherein each of the common conductive lines has a second thickness greater than a first thickness of each of the first conductive lines.

公开(公告)号：US10396277B2

公开(公告)日：2019-08-27

申请号：US15970963

申请日：2018-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Lee ,  Sang-Kuk Kim ,  Oik Kwon ,  Inho Kim ,  Jongchul Park ,  Kwangyoung Oh

IPC: H01L43/08 ,  H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L27/108 ,  H01L43/10

Abstract: A magnetic memory device includes a lower interlayer insulating layer on a substrate, and a plurality of magnetic tunnel junction patterns on the lower interlayer insulating layer and isolated from direct contact with each other in a direction extending parallel to a top surface of the substrate. The lower interlayer insulating layer includes an upper surface including a recessed surface and a top surface, the recessed surface at least partially defining an inner sidewall and a bottom surface of a recess region between adjacent magnetic tunnel junction patterns, such that the recessed surface at least partially defines the recess region. The inner sidewall is inclined at an acute angle with respect to the top surface of the substrate, and the bottom surface has a shape that is convex toward the top surface of the substrate, in direction extending perpendicular to the top surface of the substrate.