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公开(公告)号：US11756610B2
公开(公告)日：2023-09-12
申请号：US17974852
申请日：2022-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin Ju , Sangjoon Kim , Hyungwoo Lee , Seungchul Jung
IPC: G11C7/12 , G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C7/10 , G11C27/02
CPC classification number: G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C7/1006 , G11C27/02
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.
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公开(公告)号：US11587616B2
公开(公告)日：2023-02-21
申请号：US17141474
申请日：2021-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo Lee , Sangjoon Kim , Yongmin Ju
Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
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公开(公告)号：US11514980B2
公开(公告)日：2022-11-29
申请号：US17150891
申请日：2021-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin Ju , Sangjoon Kim , Hyungwoo Lee , Seungchul Jung
IPC: G11C7/12 , G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C27/02 , G11C7/10
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.
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Patent Agency Ranking
公开(公告)号：US12050886B2
公开(公告)日：2024-07-30
申请号：US17075774
申请日：2020-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen Myung , Sangjoon Kim , Seungchul Jung
CPC classification number: G06F7/5443 , G01R19/0046 , G06F13/4022 , G06F13/4282 , G06N3/04 , G11C11/161 , G11C11/1673 , G11C11/54
Abstract: A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.
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公开(公告)号：US11755900B2
公开(公告)日：2023-09-12
申请号：US17474466
申请日：2021-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangho Lee , Boyoung Seo , Sangjoon Kim , Seungchul Jung
CPC classification number: G06N3/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C11/1675 , G11C11/1657
Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.
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公开(公告)号：US11727279B2
公开(公告)日：2023-08-15
申请号：US16781328
申请日：2020-02-04
Inventor： Hyunsoo Kim , Jaeyoon Sim , Jaehan Park , Hyunwoo Son , Sangjoon Kim
CPC classification number: G06N3/088 , G06F17/18 , G06F2218/12
Abstract: A method and apparatus for performing anomaly detection by using a neural network are provided. The apparatus is configured to extract input features of an input data signal, obtain output features of the neural network by processing the input features through the neural network, obtain an error based on the input features and the output features, and determine whether the input data signal indicates an abnormal signal based on the error and a threshold.
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公开(公告)号：US20210303266A1
公开(公告)日：2021-09-30
申请号：US17075774
申请日：2020-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen Myung , Sangjoon Kim , Seungchul Jung
Abstract: A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.
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公开(公告)号：US09876791B2
公开(公告)日：2018-01-23
申请号：US14983112
申请日：2015-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chisung Bae , HaiBing Ren , YongNan Ji , Xuetao Feng , Biao Wang , Sangjoon Kim
IPC: H04L29/06 , A61B5/00 , A61B5/0452 , A61B5/117
CPC classification number: H04L63/0861 , A61B5/0452 , A61B5/117 , A61B5/7246
Abstract: A method and apparatus for authenticating a user are provided. An authentication apparatus includes a data set generator configured to generate an authentication data set by extracting waveforms from a biosignal of a user, a similarity calculator configured to match each of the extracted waveforms to registered waveforms included in a registration data set, and calculate a similarity between each of the extracted waveforms and the registered waveforms, and an auxiliary similarity calculator configured to extract a representative authentication waveform indicating a representative waveform of the extracted waveforms and a representative registration waveform indicating a representative waveform of the registered waveforms, and calculate a similarity between the representative authentication waveform and the representative registration waveform.
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