公开(公告)号：US20130254495A1

公开(公告)日：2013-09-26

申请号：US13804044

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyoum Kim ,  Jung-Hwan Choi ,  Seok-Hun Hyun

IPC: G06F13/16

CPC classification number: G06F13/1663

Abstract: A memory system includes a memory controller, and first through fourth memory modules. The first memory module is directly connected to the memory controller through a first memory bus and exchanges first data with the memory controller through the first memory bus. The second memory module is directly connected to the memory controller through a second memory bus and exchanges second data with the memory controller through the second memory bus. The third memory module is connected to the first memory module through a third memory bus and exchanges the first data with the memory controller through the first and third memory buses. The fourth memory module is connected to the second memory module through a fourth memory bus and exchanges the second data with the memory controller through the second and fourth memory buses.

Abstract translation: 存储器系统包括存储器控制器和第一至第四存储器模块。 第一存储器模块通过第一存储器总线直接连接到存储器控制器，并通过第一存储器总线与存储器控制器交换第一数据。 第二存储器模块通过第二存储器总线直接连接到存储器控制器，并通过第二存储器总线与存储器控制器交换第二数据。 第三存储器模块通过第三存储器总线连接到第一存储器模块，并通过第一和第三存储器总线与存储器控制器交换第一数据。 第四存储器模块通过第四存储器总线连接到第二存储器模块，并通过第二和第四存储器总线与存储器控制器交换第二数据。

公开(公告)号：US12033686B2

公开(公告)日：2024-07-09

申请号：US18314243

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US11423971B2

公开(公告)日：2022-08-23

申请号：US17564564

申请日：2021-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US11211102B2

公开(公告)日：2021-12-28

申请号：US17104114

申请日：2020-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US10923175B2

公开(公告)日：2021-02-16

申请号：US16230185

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US10763242B2

公开(公告)日：2020-09-01

申请号：US15995181

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon Son ,  Jung-Hwan Choi ,  Seok-Hun Hyun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L25/10 ,  H01L25/07

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

公开(公告)号：US09245605B2

公开(公告)日：2016-01-26

申请号：US14250460

申请日：2014-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Hwan Jeon ,  Yang-Ki Kim ,  Seok-Hun Hyun ,  Jung-Hwan Choi

IPC: G11C8/18 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095 ,  H03L7/10

CPC classification number: G11C8/18 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L7/10

Abstract: A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.

Abstract translation: 时钟同步电路包括延迟锁定环（DLL）和延迟锁定控制单元。 DLL被配置为通过将输入时钟信号延迟延迟时间来产生输出时钟信号，并且执行延迟锁定操作，其中延迟时间根据输出时钟信号和 输入时钟信号。 所述延迟锁定控制单元被配置为检测所述DLL的锁定状态，并且基于所确定的锁定状态来控制所述DLL。