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    High bandwidth memory and system having the same
    12.
    发明授权
    High bandwidth memory and system having the same 有权

    公开(公告)号：US11069400B1

    公开(公告)日：2021-07-20

    申请号：US16925049

    申请日：2020-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O ,  Namsung Kim ,  Sukhan Lee

    IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F9/30 ,  G06F9/38

    Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

    Managing memory device with processor-in-memory circuit to perform memory or processing operation
    16.
    发明授权
    Managing memory device with processor-in-memory circuit to perform memory or processing operation 有权

    公开(公告)号：US11663008B2

    公开(公告)日：2023-05-30

    申请号：US16814462

    申请日：2020-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

    IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

    CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

    Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

    SYSTOLIC ARRAY AND ACCELERATOR INCLUDING THE SAME
    17.
    发明申请
    SYSTOLIC ARRAY AND ACCELERATOR INCLUDING THE SAME 有权

    公开(公告)号：US20220350861A1

    公开(公告)日：2022-11-03

    申请号：US17540913

    申请日：2021-12-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

    Inventor： Seongil O ,  Wonwoo RO ,  Seihoon PARK

    IPC: G06F17/16 ,  G06F17/15

    Abstract: A systolic array and an accelerator including the same are disclosed. The systolic array may include n×n processing elements disposed in an n×n matrix (n being an integer equal to or more than at least 4), wherein the n×n processing elements perform a first convolution operation on first input data of row vectors of a first input n×n matrix and first weight data of column vectors of a first weight n×n matrix to generate n first output data, or each of at least k partial systolic arrays (k being an integer equal to or more than at least 4) constituted by dividing the n×n processing elements includes m×m processing elements disposed in an m×m matrix (m being an integer less than n and equal to or more than at least 2).

    Memory controller including plurality of address mapping tables, system on chip, and electronic device
    18.
    发明授权
    Memory controller including plurality of address mapping tables, system on chip, and electronic device 有权

    公开(公告)号：US11474950B2

    公开(公告)日：2022-10-18

    申请号：US16995935

    申请日：2020-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O

    IPC: G06F12/1009 ,  G06F12/0895

    Abstract: A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

    MEMORY MODULES AND STACKED MEMORY DEVICES
    19.
    发明申请
    MEMORY MODULES AND STACKED MEMORY DEVICES 有权

    公开(公告)号：US20210327489A1

    公开(公告)日：2021-10-21

    申请号：US17095008

    申请日：2020-11-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O ,  Jongpil Son ,  Sanghyuk Kwon

    IPC: G11C11/4078 ,  G11C11/408 ,  H01L25/065 ,  G06F21/75

    Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

    MEMORY DEVICE FOR PROCESSING OPERATION, DATA PROCESSING SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE
    20.
    发明申请
    MEMORY DEVICE FOR PROCESSING OPERATION, DATA PROCESSING SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200293319A1

    公开(公告)日：2020-09-17

    申请号：US16814462

    申请日：2020-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

    IPC: G06F9/30 ,  G06F9/32

    Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

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