公开(公告)号：US12301236B2

公开(公告)日：2025-05-13

申请号：US18331223

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon Na ,  Seonkyoo Lee ,  Seungjun Bae ,  Taesung Lee

IPC: H03K3/013 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  H03K3/017

Abstract: An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.

公开(公告)号：US20250096825A1

公开(公告)日：2025-03-20

申请号：US18772352

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daechul Jeong ,  Seonkyoo Lee ,  Taesung Lee ,  Tongsung Kim

IPC: H04B1/04 ,  H03K19/0185

Abstract: A data signal transmitter includes a standby voltage generator, which is configured to selectively output: (i) a data signal during an active operation mode, and (ii) first and second different standby voltages during a standby operation mode, and a repeater block. The repeater block includes: a first CMOS inverter configured to receive the first standby voltage during the standby operation mode, and a second CMOS inverter configured to receive the second standby voltage during the standby operation mode.

公开(公告)号：US20250095755A1

公开(公告)日：2025-03-20

申请号：US18932736

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C29/02

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.

公开(公告)号：US20250095754A1

公开(公告)日：2025-03-20

申请号：US18804617

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K5/156

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.

公开(公告)号：US11522550B2

公开(公告)日：2022-12-06

申请号：US17077891

申请日：2020-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/22 ,  H03K5/133 ,  H03L7/081 ,  H03L7/085 ,  G11C29/02

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

公开(公告)号：US10908840B2

公开(公告)日：2021-02-02

申请号：US16390077

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesung Lee ,  Junghwan Choi

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0866

Abstract: A semiconductor memory module includes data buffers that exchange first data signals with an external device, nonvolatile memory devices that are respectively connected to the data buffers through data lines, and a controller connected to the data lines. The controller receives an address, a command, and a control signal from the external device, and depending on the address, the command, and the control signal, the controller controls the data buffers through first control lines and controls the nonvolatile memory devices through second control lines.

公开(公告)号：US09767873B2

公开(公告)日：2017-09-19

申请号：US15198564

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G06F11/10 ,  G11C16/32

CPC classification number: G11C7/22 ,  G06F11/10 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/32

Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

公开(公告)号：US09576626B2

公开(公告)日：2017-02-21

申请号：US14600366

申请日：2015-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Taesung Lee

IPC: G11C7/22 ,  G11C29/02 ,  G11C29/44

CPC classification number: G11C16/32 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract translation: 非易失性存储器件包括数据通路; 以及包括连接到数据路径的多个寄存器的FIFO存储器。 多个寄存器响应于数据路径输入时钟顺序地从数据路径接收数据，并且响应于数据路径输出时钟顺序地将接收的数据输出到输入/输出焊盘。 数据路径输出时钟是通过延迟数据通道输入时钟而产生的时钟，只要延迟时间。