Semiconductor memory device
    11.
    发明授权

    公开(公告)号:US12213302B2

    公开(公告)日:2025-01-28

    申请号:US17725069

    申请日:2022-04-20

    Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME

    公开(公告)号:US20240397726A1

    公开(公告)日:2024-11-28

    申请号:US18655488

    申请日:2024-05-06

    Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.

    SEMICONDUCTOR DEVICES
    13.
    发明公开

    公开(公告)号:US20240015975A1

    公开(公告)日:2024-01-11

    申请号:US18108722

    申请日:2023-02-13

    CPC classification number: H10B51/20 H10B51/30

    Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.

    SEMICONDUCTOR DEVICES
    15.
    发明公开

    公开(公告)号:US20230413557A1

    公开(公告)日:2023-12-21

    申请号:US18183903

    申请日:2023-03-14

    CPC classification number: H10B43/27 H10B41/27

    Abstract: A semiconductor device includes a source structure, a plurality of gate electrodes on the source structure. The plurality of gate electrodes are stacked and spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction, and a channel structure in a channel hole extends through the plurality of gate electrodes and in the first direction, the channel structure including a first dielectric layer on a sidewall of the channel hole, a second dielectric layer on the first dielectric layer opposite the sidewall of the channel hole, a channel layer on the second dielectric layer opposite the sidewall of the channel hole, and a filling insulating layer on the channel layer opposite the sidewall of the channel hole, and further including a channel pad layer in a region including an upper end of the channel hole, wherein the second dielectric layer includes a ferroelectric material, and wherein the channel pad layer is in contact with an internal side surface of the first dielectric layer and covers an upper surface of the second dielectric layer, an upper surface of the channel layer, and an upper surface of the filling insulating layer.

    SEMICONDUCTOR DEVICES
    16.
    发明公开

    公开(公告)号:US20230354580A1

    公开(公告)日:2023-11-02

    申请号:US18115116

    申请日:2023-02-28

    CPC classification number: H10B12/20 H10B12/01

    Abstract: A semiconductor device includes a gate electrode on a substrate, a memory body structure extending through the gate electrode, a source layer at an end portion of the memory body structure and including germanium doped with p-type impurities, and a drain layer at another end portion of the memory body structure and including a metal or a metal alloy. The memory body structure may include a body including undoped polysilicon, a charge storage pattern on a sidewall of the body, and a blocking pattern on an outer sidewall of the charge storage pattern and contacting the gate electrode.

    Semiconductor memory device
    17.
    发明授权

    公开(公告)号:US11621264B2

    公开(公告)日:2023-04-04

    申请号:US16999378

    申请日:2020-08-21

    Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

    Method and device for controlling transmission power of terminal in beamforming system

    公开(公告)号:US11570729B2

    公开(公告)日:2023-01-31

    申请号:US17496386

    申请日:2021-10-07

    Abstract: The present disclosure relates to a communication technique for convergence of a 5G communication system for supporting a higher data transmission rate beyond a 4G system with an IoT technology, and a system therefor. The present disclosure may be applied to an intelligent service (for example, smart home, smart building, smart city, smart car or connected car, health care, digital education, retail business, security and safety-related service, etc.) on the basis of a 5G communication technology and an IoT related technology. The present invention relates to a method for controlling power of a terminal in a beamforming system and, specifically, provides a method for supporting control of uplink power of a terminal according to a beam change.

    SEMICONDUCTOR MEMORY DEVICES
    19.
    发明申请

    公开(公告)号:US20220108741A1

    公开(公告)日:2022-04-07

    申请号:US17362138

    申请日:2021-06-29

    Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

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