公开(公告)号：US20240363573A1

公开(公告)日：2024-10-31

申请号：US18764827

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Myungsam KANG

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.

公开(公告)号：US20240178122A1

公开(公告)日：2024-05-30

申请号：US18226352

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Sangjin BAEK ,  Kyoung Lim SUK ,  Shang-Hoon SEO ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.

公开(公告)号：US20240047303A1

公开(公告)日：2024-02-08

申请号：US18361099

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Don MUN ,  Geun Woo KIM ,  Tae-Young LEE

IPC: H01L23/46 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/46 ,  H01L25/0655 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/08 ,  H01L2224/08235 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package structure include a silicon substrate, a plurality of dies on the silicon substrate, a mold layer between the plurality of dies, a metal layer covering an upper side of the mold layer and at least a part of upper sides of each of the plurality of dies, and including an opening that exposes a part of the upper side of at least one die among the plurality of dies, and a temperature controller configured to control a temperature of the plurality of dies, the temperature controller including a body defining a circulation region configured to circulate a fluid for controlling the temperature of the plurality of dies, and a passage part configured to allow the fluid to flow into or out of the circulation region, and the fluid in the circulation region being in direct contact with exposed upper sides of the plurality of dies.

公开(公告)号：US20230275056A1

公开(公告)日：2023-08-31

申请号：US18141838

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Myungsam KANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/214

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.