公开(公告)号：US11194655B2

公开(公告)日：2021-12-07

申请号：US16775587

申请日：2020-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Kim ,  Inyoung Kim ,  Jonghwa Kim ,  Chanik Park

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F3/06

Abstract: A storage device includes a non-volatile memory including a plurality of memory blocks and a storage controller configured to control a read operation of the non-volatile memory. The storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and power-on time information indicating a power-on time point at which the storage device is powered on, when the storage device is switched from a power-off state to a power-on state. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

公开(公告)号：US20250008737A1

公开(公告)日：2025-01-02

申请号：US18882427

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Shinhwan Kang ,  Jihwan Kim ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

公开(公告)号：US11147086B2

公开(公告)日：2021-10-12

申请号：US16565578

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihwan Kim ,  Kyunghoon Lee ,  Soomin Lee ,  Hyejeong Kim ,  Sangho Lee ,  Mooyoung Kim

IPC: H04W72/12 ,  H04W76/30 ,  H04W64/00 ,  H04W76/10 ,  H04W88/06

Abstract: An electronic device is provided. The electronic device includes a first processor configured to perform wireless communication with a local area data network (LADN), and a second processor electrically connected with the first processor. The first processor is configured to receive a first message from the LADN indicating that a wireless communication session with the LADN is deactivated because the electronic device has departed from a geographic service area of the LADN, after receiving the first message, and transmit a second message to the second processor indicating that the wireless communication session is deactivated. The second processor is configured to terminate generation of a data packet for uplink transmission after receiving the second message.

公开(公告)号：US20250014997A1

公开(公告)日：2025-01-09

申请号：US18892906

申请日：2024-09-23

Applicant: Samsung electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L29/423 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US12120882B2

公开(公告)日：2024-10-15

申请号：US17241343

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Shinhwan Kang ,  Jihwan Kim ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

公开(公告)号：US20240128055A1

公开(公告)日：2024-04-18

申请号：US18232992

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunbae Kim ,  Jihwan Kim ,  Sangki Nam ,  Daeun Son ,  Seungbo Shim ,  Juho Lee ,  Hyunjae Lee ,  Hyunhak Jeong

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32128 ,  H01J2237/0473

Abstract: A method of manufacturing a semiconductor device includes placing a wafer in a plasma chamber, the chamber including a first power generator configured to generate plasma ions in the chamber, and a second power generator configured to accelerate the plasma ions toward the wafer, generating a radio frequency (RF) signal having a repeated periodic sinusoidal waveform in an on state and a steady off state by the first power generator, and generating a direct current (DC) bias signal having a repeated periodic non-sinusoidal waveform in an on state and a steady off state by the second power generator. The RF signal and the DC bias signal are offset from each other. The method further includes performing a plasma process on a layer on the wafer, using the RF signal and DC bias signal.

公开(公告)号：US11791262B2

公开(公告)日：2023-10-17

申请号：US17475128

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyoon Kim ,  Jeongyong Sung ,  Sanghun Chun ,  Jihwan Kim ,  Sunghee Chung ,  Jeehoon Han

IPC: H01L23/528 ,  H01L29/423 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L29/42356 ,  H10B43/27

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

公开(公告)号：US20230274783A1

公开(公告)日：2023-08-31

申请号：US18143907

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  G11C16/0483 ,  H01L2924/14511 ,  H01L2225/06541 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US11670378B2

公开(公告)日：2023-06-06

申请号：US17499533

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

公开(公告)号：US12230330B2

公开(公告)日：2025-02-18

申请号：US18143907

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongwoo Lee ,  Chaehoon Kim ,  Jihwan Kim ,  Jungho Song

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.