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18 条记录 (耗时 0.012 秒)

    Automated calling system with database updating
    12.
    发明授权
    Automated calling system with database updating 失效
    具有数据库更新的自动呼叫系统

    公开(公告)号：US5559867A

    公开(公告)日：1996-09-24

    申请号：US262923

    申请日：1994-06-20

    申请人： Al Langsenkamp ,  William D. Arnold ,  Scott Arnold

    发明人： Al Langsenkamp ,  William D. Arnold ,  Scott Arnold

    IPC分类号： H04M3/02 ,  H04M3/42 ,  H04M3/46 ,  H04M3/487 ,  H04M3/493 ,  H04M3/51 ,  H04M3/44

    CPC分类号： H04M3/5158 ,  H04M3/02 ,  H04M3/42 ,  H04M3/46 ,  H04M3/465 ,  H04M3/487 ,  H04M3/5166 ,  H04M2203/2016 ,  H04M2203/205 ,  H04M2242/04 ,  H04M3/493 ,  H04M3/4931

    摘要： An automated phone calling system includes a database comprising phone numbers and one or more data fields associated with each phone number. Phone numbers (callees) in the database are selected based on the data fields associated therewith. A recorded voice message is transmitted to callees through a plurality of outgoing phone lines, and callees are prompted to enter one of several TOUCH TONE codes, which is recorded. The database record for the callee is automatically updated based on the TOUCH TONE response code, so that the updated field may be used to select whether to send a future call to the callee.

    摘要翻译： 自动电话呼叫系统包括包括电话号码和与每个电话号码相关联的一个或多个数据字段的数据库。 基于与其相关联的数据字段来选择数据库中的电话号码（被叫方）。 记录的语音消息通过多个输出电话线路被发送到被呼叫者，并且被叫被提示进入记录的几个TOUCH TONE码之一。 基于TOUCH TONE响应码自动更新被叫方的数据库记录，以便可以使用更新的字段来选择是否将来呼叫发送到被叫方。

    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
    13.
    发明授权
    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system 失效
    用于确保多处理器系统中的多个高速缓冲存储器与主存储器之间的数据一致性的方案

    公开(公告)号：US5222224A

    公开(公告)日：1993-06-22

    申请号：US727296

    申请日：1991-07-09

    申请人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    发明人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. In particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "stale" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor--in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.

    摘要翻译： 提供了一种用于在多处理器计算机系统中确保多个单独处理器高速缓冲存储器与主存储器之间的数据一致性的方法，其能够（1）检测何时发生一组预定义数据不一致状态之一作为数据事务 正在处理请求，以及（2）校正数据不一致状态，以便以正确和一致的方式执行操作。 特别地，该方法适于解决两种数据不一致状态：（1）当要写入的位置存在于一些处理器单元的高速缓存中时，请求从系统单元到主存储器的操作 - 如此 一种情况下，缓存中的数据是“陈旧”的，并且通过防止相关联的处理器使用“过时”数据来避免数据不一致; 和（2）当通过系统单元请求主存储器的读取操作并且可以将待读取的位置写入或已经写入一些处理器的高速缓存中时 - 在这种情况下，主存储器中的数据是“过时的” “并且通过确保返回到请求单元的数据是高速缓存中的更新数据来避免数据不一致。 在基于SCU的多处理系统中检测到上述数据不一致状态之一的存在，通过为SCU提供用于维护每个处理器高速缓存的高速缓存目录的副本的装置。 SCU连续地将伴随存储器访问请求的地址数据与存储在SCU高速缓存目录中的内容进行比较，以便确定指示数据不一致性的预定义条件的存在，并且随后执行相应的预定义修补序列。

    Method and apparatus for displaying an image
    14.
    发明授权
    Method and apparatus for displaying an image 有权
    用于显示图像的方法和装置

    公开(公告)号：US09026946B2

    公开(公告)日：2015-05-05

    申请号：US13204838

    申请日：2011-08-08

    申请人： Alen Mujkic ,  Scott Arnold ,  John Paul Hayman

    发明人： Alen Mujkic ,  Scott Arnold ,  John Paul Hayman

    IPC分类号： G06F3/033 ,  G09G5/00 ,  G06F9/44

    CPC分类号： G09G5/00 ,  G06F9/451 ,  G09G2340/0407 ,  G09G2340/0442 ,  G09G2340/0464 ,  G09G2340/0492 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/14

    摘要： An electronic device and a method of operation thereof for facilitating the provision of an image as a background wallpaper of a user interface for display on a display of an electronic device, the device being configured to display the user interface and wallpaper in first and second different orientations during use, comprising: generating, based on the image, a first thumbnail representation of the appearance of the display having the image as the background wallpaper in a first orientation; generating, based on the image, a second thumbnail representation of the appearance of the display having the image as the background wallpaper in a second orientation; and simultaneously displaying on the display the first and second thumbnails.

    摘要翻译： 一种电子设备及其操作方法，用于便于将图像提供为用于在电子设备的显示器上显示的用户界面的背景壁纸，该设备被配置为在第一和第二不同的显示器中显示用户界面和壁纸 使用中的取向包括：基于图像生成具有作为第一方向的背景壁纸的图像的显示的外观的第一缩略图表示; 基于所述图像生成具有作为所述背景壁纸的所述图像的显示的外观的第二缩略图表示; 并且同时在显示器上显示第一和第二缩略图。

    Stuffed toy
    17.
    外观设计
    Stuffed toy 有权
    毛绒玩具

    公开(公告)号：USD631517S1

    公开(公告)日：2011-01-25

    申请号：US29349714

    申请日：2010-04-26

    申请人： Scott Arnold

    设计人： Scott Arnold

    Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits
    18.
    发明授权
    Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits 失效
    使用锁定目录的多处理器系统中的存储器访问操作的同步和处理

    公开(公告)号：US5175837A

    公开(公告)日：1992-12-29

    申请号：US306541

    申请日：1989-02-03

    申请人： Scott Arnold ,  James Kann ,  Stephen J. DeLaHunt ,  Tryggve Fossum

    发明人： Scott Arnold ,  James Kann ,  Stephen J. DeLaHunt ,  Tryggve Fossum

    IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/177

    CPC分类号： G06F9/52

    摘要： All monitoring and control of locked memory access requests in a multiprocessing computer system is handled by a system control unit (SCU) which controls the parallel operation of a plurality of central processing units (CPUs) and I/O units relative to a common main memory. Locking granularity is defined at the level of individual cache blocks for the CPUs, and the cache blocks also represent the unit of memory allocation in the computer system. The SCU is provided with a lock directory defined by a plurality of lock bits so that addresses in the same block of memory are mapped to the same location in the lock directory. Incoming lock requests for a given memory location are processed by interrogating the corresponding lock bit in the lock directory in the SCU by using the associated memory address as an index into the directory. If the lock bit is not set, the lock request is granted. The lock bit is subsequently set and maintained in that state until the unit requesting the lock has completed its memory access operation and sends an "unlock" request. If the interrogated lock bit is found to be set, the lock request is denied and the requesting port is notified of the denial. Fairness for the processing of denied lock requests is insured by a reserve list onto which denied requests are sequentially positioned on a first-come-first-served basis.