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公开(公告)号：US20180341594A1
公开(公告)日：2018-11-29
申请号：US15606502
申请日：2017-05-26
发明人： Timothy Canepa , Jeffrey Munsil , Jackson Ellis , Mark Ish
IPC分类号： G06F12/1009 , G06F3/06
摘要： Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.
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公开(公告)号：US20170242794A1
公开(公告)日：2017-08-24
申请号：US15048080
申请日：2016-02-19
发明人： Horia Cristian Simionescu , Balakrishnan Sundararaman , Shashank Nemawarkar , Larry Stephen King , Mark Ish , Shailendra Aulakh
CPC分类号： G06F12/0806 , G06F12/0804 , G06F12/0895 , G06F12/1018 , G06F12/1081 , G06F12/122 , G06F2212/1024 , G06F2212/604 , G06F2212/621 , G06F2212/656
摘要： In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.
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公开(公告)号：US20220075729A1
公开(公告)日：2022-03-10
申请号：US17528977
申请日：2021-11-17
IPC分类号： G06F12/0873 , G06F12/128 , G06F12/02
摘要： A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
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公开(公告)号：US10423500B2
公开(公告)日：2019-09-24
申请号：US15170709
申请日：2016-06-01
发明人： David S. Ebsen , Kevin A. Gomez , Mark Ish , Daniel J. Benjamin
摘要： Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.
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公开(公告)号：US20180349285A1
公开(公告)日：2018-12-06
申请号：US15609758
申请日：2017-05-31
发明人： Mark Ish , Steven S. Williams , Jeffrey Munsil
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F2212/7201
摘要： Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.
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公开(公告)号：US20180349148A1
公开(公告)日：2018-12-06
申请号：US15608127
申请日：2017-05-30
发明人： Mark Ish , Timothy Canepa , David S. Ebsen
IPC分类号： G06F9/44 , G06F12/0888
摘要： A data storage device may consist of a non-volatile memory having rewritable in-place memory cells each with a read-write asymmetry. The non-volatile memory can store boot data that is subsequently loaded by a selection module of the data storage device. The selection module may bypass a memory buffer of the data storage device to load the boot data.
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公开(公告)号：US10147501B1
公开(公告)日：2018-12-04
申请号：US15607784
申请日：2017-05-30
发明人： David S. Ebsen , Mark Ish , Timothy Canepa
IPC分类号： G11C7/10 , G11C29/00 , G06F12/02 , G11C11/406 , G11C7/18 , G11C8/14 , G06F12/1045
CPC分类号： G11C29/789 , G06F12/0238 , G06F12/1054 , G06F12/1063 , G11C7/18 , G11C8/14 , G11C11/40607
摘要： A data storage device may consist of a non-volatile memory connected to a selection module. The non-volatile memory can have a rewritable in-place memory cell that has a read-write asymmetry. The selection module can dedicate a portion of the non-volatile memory to a data map that can be self-contained along with reactively and proactively altered by the selection module.
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公开(公告)号：US10068663B1
公开(公告)日：2018-09-04
申请号：US15607801
申请日：2017-05-30
发明人： David S. Ebsen , Mark Ish , Timothy Canepa
摘要： A non-volatile memory may be resident in a data storage device. The non-volatile memory can consist of a rewritable in-place memory cell having a read-write asymmetry. The non-volatile memory may be divided into a first group of tiers with a selection module of the data storage device prior to adapting to an event by altering the non-volatile memory into a second group of tiers. The first and second groups of tiers being different.
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公开(公告)号：US20180081558A1
公开(公告)日：2018-03-22
申请号：US15709681
申请日：2017-09-20
CPC分类号： G06F3/0607 , G06F3/0655 , G06F3/0688 , G06F13/4022 , G06F13/4282 , G06F2213/0026
摘要： Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.
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公开(公告)号：US10564865B2
公开(公告)日：2020-02-18
申请号：US15077420
申请日：2016-03-22
IPC分类号： G06F3/06 , G06F12/08 , G06F12/0866
摘要： Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.
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