公开(公告)号：US09424890B2

公开(公告)日：2016-08-23

申请号：US14951937

申请日：2015-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki

IPC: G11C11/24 ,  G11C5/10 ,  H01L27/06 ,  H01L27/108 ,  G11C7/12

CPC classification number: G11C5/10 ,  G11C7/12 ,  G11C11/405 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.

Abstract translation: 提供能够抑制不正确的数据读出的半导体器件。 在包括第一晶体管，第二晶体管和第三晶体管的存储单元中，例如，当数据被写入时，第四布线的电位被设置为GND，并且例如在读出数据时将电位设置为VDD。 注意，例如，当写入数据和数据被读出时，第三布线的电位被设置为GND。 当读出数据时，第一晶体管截止，使得第一电容器和第四电容器串联连接。 在该状态下，第二电容器的第二电极的电位增加，因此累积在第二电容器中的电荷的一部分转移到第一电容器，使得节点的电位增加。

公开(公告)号：US09270173B2

公开(公告)日：2016-02-23

申请号：US14580279

申请日：2014-12-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei Takahashi ,  Yoshiaki Ito ,  Hiroki Inoue ,  Tatsuji Nishijima

IPC: G05F1/00 ,  H02M3/156 ,  H01L27/12 ,  H01L29/786 ,  H02M3/155

CPC classification number: H02M3/156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869 ,  H02M3/155

Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.

Abstract translation: 提供了具有高可靠性的DC转换器电路。 DC转换器电路包括：电感器，被配置为根据流动电流的变化产生电动势; 包括栅极，源极和漏极的晶体管，其被配置为通过导通或关断来控制电感器中的电动势的产生; 当晶体管截止时处于导通状态的整流器; 以及被配置为控制晶体管的导通和截止的控制电路。 晶体管包括作为沟道形成层的氢浓度小于或等于5×1019原子/ cm3的氧化物半导体层。

公开(公告)号：US09245650B2

公开(公告)日：2016-01-26

申请号：US14199584

申请日：2014-03-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kei Takahashi ,  Tatsuya Onuki

IPC: H03L5/00 ,  G11C27/02 ,  H03K5/24

CPC classification number: H03K5/2481 ,  G11C27/024 ,  G11C27/026 ,  H03K5/249

Abstract: A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized.

公开(公告)号：US20150311323A1

公开(公告)日：2015-10-29

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: H01L29/66 ,  H01L21/425 ,  H01L27/115 ,  H01L21/441 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US20140269063A1

公开(公告)日：2014-09-18

申请号：US14201068

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/08

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 放电位线的电荷，通过用于写入数据的晶体管对位线的电位进行充电，并且通过充电而改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US12176810B2

公开(公告)日：2024-12-24

申请号：US17621338

申请日：2020-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kousuke Sasaki ,  Yuto Yakubo ,  Kei Takahashi

IPC: H02M3/156 ,  H01L27/12 ,  H01L29/786 ,  H02H7/18

Abstract: A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.

公开(公告)号：US11937007B2

公开(公告)日：2024-03-19

申请号：US17628293

申请日：2020-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Seiichi Yoneda ,  Yusuke Negoro ,  Takahiko Ishizu ,  Hidetomo Kobayashi

IPC: H04N25/77 ,  H01L27/146 ,  H04N25/50 ,  H04N25/75 ,  H10B12/00 ,  H10K39/32

CPC classification number: H04N25/77 ,  H04N25/50 ,  H01L27/14645 ,  H04N25/75 ,  H10B12/00 ,  H10K39/32

Abstract: An imaging device having a motion detecting function and an image processing function is provided. The imaging device can detect a difference between a reference frame image and a comparative frame image, and can switch from a motion detecting mode to a normal image capturing mode when a significant difference is detected. A low-frame-rate operation in the motion detecting mode can reduce power consumption. Moreover, the imaging device has an image recognition function in combination with the motion detecting function, so that switching from the motion detecting mode to the normal image capturing mode can be performed when a particular image is recognized.

公开(公告)号：US11276711B2

公开(公告)日：2022-03-15

申请号：US15821006

申请日：2017-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Fumika Akasawa

IPC: G11C19/00 ,  H01L27/12 ,  H03K3/356 ,  G09G3/36 ,  G09G3/3266 ,  G09G3/3233 ,  G11C19/28 ,  G11C19/14 ,  G06F3/041

Abstract: A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.

公开(公告)号：US10964700B2

公开(公告)日：2021-03-30

申请号：US16885742

申请日：2020-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Fumika Akasawa ,  Hiroki Inoue ,  Takashi Nakagawa ,  Yoshiyuki Kurokawa

IPC: H01L33/00 ,  H01L21/00 ,  H01L27/108

Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.

公开(公告)号：US10277181B2

公开(公告)日：2019-04-30

申请号：US15685079

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue

IPC: H03F3/45 ,  G09G5/00 ,  H03K19/0185 ,  G05F3/26 ,  H03K19/003 ,  G09G3/36 ,  G09G3/20 ,  H03K19/00

Abstract: To reduce power consumption and perform high-speed switching in boosting a voltage to a desired voltage. A semiconductor device includes a first buffer circuit, a level-shift circuit, and a second buffer circuit. The first buffer circuit includes a tri-state buffer circuit. The tri-state buffer circuit has a function of making each of an output of an input signal and an output of an inverted input signal into a resting state in response to a standby signal. The level-shift circuit includes a current mirror circuit, a differential amplifier circuit, and a switch circuit. The differential amplifier circuit has a function of controlling a current flowing through the current mirror circuit using the input signal and the inverted input signal as differential signals. The switch circuit has a function of making a current flowing through the differential amplifier circuit into a resting state in response to the standby signal.