公开(公告)号：US20150091001A1

公开(公告)日：2015-04-02

申请号：US14479776

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Takayuki SAITO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.

Abstract translation: 在小型化晶体管中，需要栅极绝缘层来减小其厚度; 然而，在栅绝缘层是单层氧化硅膜的情况下，由于隧穿电流（即栅极漏电流）的增加，可能会发生栅极绝缘层变薄的物理极限。 通过使用栅极绝缘层使用相对介电常数高于或等于10的高k膜，减小了小型化晶体管的栅极漏电流。 通过使用高k膜作为相对介电常数高于与氧化物半导体层接触的第二绝缘层的第一绝缘层的第一绝缘层，栅绝缘层的厚度可以比栅的厚度薄 根据氧化硅膜考虑的绝缘层。

公开(公告)号：US20140252347A1

公开(公告)日：2014-09-11

申请号：US14281031

申请日：2014-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Mizuho SATO

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78606

Abstract: Disclosed is a semiconductor device with a transistor in which an oxide semiconductor is used. An insulating layer on a back channel side of the oxide semiconductor layer has capacitance of lower than or equal to 2×10−4 F/m2. For example, in the case of a top-gate transistor, a base insulating layer has capacitance of lower than or equal to 2×10−4 F/m2, whereby the adverse effect of an interface state between the substrate and the base insulating layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.

Abstract translation: 公开了具有使用氧化物半导体的晶体管的半导体器件。 氧化物半导体层的背面通道侧的绝缘层的电容为2×10 -4 F / m 2以下。 例如，在顶栅晶体管的情况下，基极绝缘层具有小于或等于2×10 -4 F / m 2的电容，由此衬底和基极绝缘层之间的界面态的不利影响 可以减少 因此，可以制造电特性波动小，可靠性高的半导体装置。

公开(公告)号：US20240113230A1

公开(公告)日：2024-04-04

申请号：US18530404

申请日：2023-12-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/42392 ,  H01L29/78696

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

公开(公告)号：US20230389262A1

公开(公告)日：2023-11-30

申请号：US18233172

申请日：2023-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuta ENDO ,  Junpei SUGAO

IPC: H10B12/00 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

CPC classification number: H10B12/00 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

公开(公告)号：US20220020785A1

公开(公告)日：2022-01-20

申请号：US17491702

申请日：2021-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO

IPC: H01L27/12 ,  G02F1/1368

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.

公开(公告)号：US20210242220A1

公开(公告)日：2021-08-05

申请号：US17236115

申请日：2021-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomoaki ATSUMI ,  Yuta ENDO

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

公开(公告)号：US20210126114A1

公开(公告)日：2021-04-29

申请号：US17073520

申请日：2020-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/425 ,  H01L21/477 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

公开(公告)号：US20190237586A1

公开(公告)日：2019-08-01

申请号：US16354394

申请日：2019-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/092 ,  H01L27/06 ,  H01L29/49 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/76826 ,  H01L21/02321 ,  H01L21/76802 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

公开(公告)号：US20170033226A1

公开(公告)日：2017-02-02

申请号：US15217080

申请日：2016-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Motomu KURATA ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/8258 ,  H01L22/12 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

Abstract translation: 提供一种包括具有小型化结构的晶体管的半导体器件。 第一绝缘体设置在堆叠中，其中半导体，第一导体和第二导体以该顺序堆叠。 在第一绝缘体上形成蚀刻掩模。 使用蚀刻掩模，蚀刻第一绝缘体和第二导体，直到暴露出第一导体。 在蚀刻第一导体直到半导体暴露以形成宽度小于第二导体的沟槽之后，依次形成第二绝缘体和第三导体。

公开(公告)号：US20170005203A1

公开(公告)日：2017-01-05

申请号：US15192312

申请日：2016-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

Abstract translation: 提供了一种小型化的晶体管。 在半导体上的第三绝缘体上形成第一层; 在第一层上形成第二层; 在第二层上形成蚀刻掩模; 使用蚀刻掩模蚀刻第二层，直到第一层暴露以形成第三层; 选择性生长层形成在第三层的顶表面和侧表面上; 使用第三层和选择性生长层来蚀刻第一层，直到暴露第三绝缘体以形成第四层; 并且使用第三层，选择性生长层和第四层蚀刻第三绝缘体，直到半导体暴露以形成第一绝缘体。