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    Ultra small-sized SOI MOSFET and method of fabricating the same
    12.
    发明授权
    Ultra small-sized SOI MOSFET and method of fabricating the same 有权
    超小型SOI MOSFET及其制造方法

    公开(公告)号：US06723587B2

    公开(公告)日：2004-04-20

    申请号：US10331568

    申请日：2002-12-31

    Applicant: Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

    Inventor： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

    IPC: H01L2184

    CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78609

    Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

    Abstract translation: 提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。 该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分 第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质 在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层 形成，形成接触孔以露出栅电极，源极区和漏极 区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

    Ultra-thin MO-C film transistor
    13.
    发明授权
    Ultra-thin MO-C film transistor 失效
    超薄MO-C薄膜晶体管

    公开(公告)号：US5883419A

    公开(公告)日：1999-03-16

    申请号：US850013

    申请日：1997-05-01

    Applicant: Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

    Inventor： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

    IPC: H01L41/00 ,  H01L45/00 ,  B02J17/40 ,  B05D3/06

    CPC classification number: H01L45/00

    Abstract: A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

    Abstract translation: 根据本发明的晶体管包括用作电子流的通道的超薄Mo-C膜，其中薄金属膜的两端分别用作晶体管的源极和漏极端子; 形成在Mo-C膜上的压电膜，用于根据由栅极电压提供的施加的电场产生力; 以及形成在作为施加栅极电压的晶体管的栅极的压电膜上产生施加的电场的电极膜; 并且其中源极和漏极端子之间的Mo-C膜的电阻根据施加的栅极电压产生的力而改变。 该晶体管可以用作具有层叠结构的三维集成电路的元件。

    Apparatus for receiving heterogeneous materials
    15.
    发明授权
    Apparatus for receiving heterogeneous materials 有权

    公开(公告)号：US11053061B2

    公开(公告)日：2021-07-06

    申请号：US14124079

    申请日：2011-11-30

    Applicant: Seong-Jae Lee

    Inventor： Seong-Jae Lee

    IPC: B65D25/08 ,  B65D81/32 ,  B65D51/28 ,  B65D51/22 ,  B29C45/16

    Abstract: The prevent invention relates to an apparatus for receiving heterogeneous materials which is coupled to a hole part of a container in which a content such as liquid or the like is contained. The apparatus for receiving the heterogeneous materials includes a main body coupled and fixed to a hole part of a container and a receiving part having a storage space within the main body. In the inner storage space of the receiving part, a foldable connection part is disposed in an upper portion of the storage space and an opening part formed below the foldable connection part breaks a receiving part sealing part sealing a lower end of the receiving part to allow a content within the storage space of the receiving part to drop down into the container, thereby mixing the heterogeneous materials. Here, a foldable soft resin may be added to the foldable connection part.

    CONNECTION DIE COUPLED WITH CONTAINER NECK IN USE
    17.
    发明申请
    CONNECTION DIE COUPLED WITH CONTAINER NECK IN USE 审中-公开
    连接器与使用者使用的集装箱连接

    公开(公告)号：US20150158621A1

    公开(公告)日：2015-06-11

    申请号：US14412857

    申请日：2010-11-19

    Applicant: Jeong-Min Lee ,  Seong-Jae Lee

    Inventor： Jeong-Min Lee ,  Seong-Jae Lee

    IPC: B65D1/02

    CPC classification number: B65D1/0246 ,  B65D41/0421 ,  B65D45/325 ,  B65D47/123 ,  B65D47/243 ,  B65D2101/0023 ,  B65D2251/08

    Abstract: Disclosed is a connection device to be coupled with a container neck in different standards for use. The connection device is formed with a mouth part at the upper side and a screw thread part at the lower side. The mouth part at the upper portion of the connection device is formed in a screw thread or other shape in the standard corresponding to a bottle lid, and the inside of the screw thread part is formed with a screw thread corresponding to the standard of the container neck. The screw thread is integrally formed or an elastic screw thread is additionally added for the coupling with the necks of a plurality of containers.

    Abstract translation: 公开了一种与容器颈部联接以便使用不同标准的连接装置。 连接装置在上侧形成有口部，在下侧形成有螺纹部。 连接装置的上部的口部形成为与瓶盖对应的标准的螺纹或其他形状，螺纹部的内部形成有与容器的标准对应的螺纹 颈部。 螺纹是整体形成的，或者另外添加弹性螺纹用于与多个容器的颈部的联接。

    Magnetoelastic torque sensor with ambient field rejection
    18.
    发明授权
    Magnetoelastic torque sensor with ambient field rejection 失效
    具有环境场阻抗的磁弹力矩传感器

    公开(公告)号：US08087304B2

    公开(公告)日：2012-01-03

    申请号：US12403992

    申请日：2009-03-13

    Applicant: Seong-Jae Lee

    Inventor： Seong-Jae Lee

    IPC: G01L3/14 ,  G01L3/00 ,  G01B7/14

    CPC classification number: G01L3/102 ,  G01R33/07

    Abstract: The present invention involves a method and apparatus for canceling the effects of magnetic field noise in a torque sensor by placing three sets of magnetic field sensors around a shaft, the first set of field sensors being placed in the central region of the shaft and the second and third sets of field sensors being placed on the right side and left side of the field sensors placed at the central region, respectively. A torque-induced magnetic field is not cancelled with this arrangement of field sensors but a magnetic near field from a near field source is cancelled.

    Abstract translation: 本发明涉及一种用于通过将三组磁场传感器放置在轴周围来消除扭矩传感器中的磁场噪声的影响的方法和装置，第一组场传感器被放置在轴的中心区域中，而第二组 并且第三组场传感器分别放置在放置在中心区域的场传感器的右侧和左侧。 通过这种现场传感器的布置，扭矩感应磁场不被抵消，而来自近场源的磁场近场被取消。

    Method for fabricating Schottky barrier tunnel transistor
    20.
    发明授权
    Method for fabricating Schottky barrier tunnel transistor 失效
    制造肖特基势垒隧道晶体管的方法

    公开(公告)号：US07745316B2

    公开(公告)日：2010-06-29

    申请号：US11930902

    申请日：2007-10-31

    Applicant: Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    Inventor： Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    IPC: H01L21/28 ,  H01L21/44

    CPC classification number: H01L29/78618 ,  H01L29/7839

    Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

    Abstract translation: 提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。 一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

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