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53 条记录 (耗时 0.026 秒)

    Liquid crystal display
    11.
    发明授权
    Liquid crystal display 有权
    液晶显示器

    公开(公告)号：US07218371B2

    公开(公告)日：2007-05-15

    申请号：US11166010

    申请日：2005-06-24

    申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

    发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

    IPC分类号： G02F1/1345 ,  G02F1/1343

    CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

    摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.

    摘要翻译： 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于周边区域中的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分处停止，并且筛选由杂质离子引起的图像缺陷区域 与黑色矩阵。

    Nonvolatile semiconductor memories with a cell structure suitable for a high speed operation and a low power supply voltage
    14.
    发明授权
    Nonvolatile semiconductor memories with a cell structure suitable for a high speed operation and a low power supply voltage 失效
    具有适用于高速运行和低电源电压的电池结构的非易失性半导体存储器

    公开(公告)号：US5528537A

    公开(公告)日：1996-06-18

    申请号：US505038

    申请日：1995-07-21

    申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

    发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

    IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

    摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

    摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

    Nonvolatile memory device including multi-ECC circuit
    15.
    发明授权
    Nonvolatile memory device including multi-ECC circuit 失效
    非易失性存储器件包括多ECC电路

    公开(公告)号：US5469450A

    公开(公告)日：1995-11-21

    申请号：US099331

    申请日：1993-07-30

    申请人： Sung-Hee Cho ,  Hyong-Gon Lee

    发明人： Sung-Hee Cho ,  Hyong-Gon Lee

    IPC分类号： G11C17/00 ,  G06F11/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G06F11/1076

    摘要： A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

    摘要翻译： 一种包含副存储器阵列和不同的相关联的外围子阵列电路的非易失性存储器件，其包含根据子阵列类似地定位的错误检查和校正电路。 存储器件被配置为使得单个掩模改变允许将器件制造为普通模式器件或页模式器件。

    Data output control circuit
    16.
    发明授权
    Data output control circuit 失效
    数据输出控制电路

    公开(公告)号：US5357530A

    公开(公告)日：1994-10-18

    申请号：US934249

    申请日：1992-08-25

    申请人： Hyong-Gon Lee ,  Sung-Hee Cho

    发明人： Hyong-Gon Lee ,  Sung-Hee Cho

    IPC分类号： G11C11/409 ,  G06F11/10 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/22

    摘要： A data output control circuit of a semiconductor memory device. The data output control circuit comprises an input signal detector for detecting a desired signal, a controller for selecting one of a plurality of data output buffers and a data output controller for driving the selected data output buffer. A signal for driving and controlling the data output buffer is enabled after the data of a given memory cell is supplied to an input terminal of the data output buffer so that any unnecessary transition operation of data can be eliminated to reduce the current dissipation of a semiconductor memory chip and to prevent the deterioration of data access time for the purpose of improving the yield of the semiconductor memory chip.

    摘要翻译： 半导体存储器件的数据输出控制电路。 数据输出控制电路包括用于检测所需信号的输入信号检测器，用于选择多个数据输出缓冲器中的一个的控制器和用于驱动所选数据输出缓冲器的数据输出控制器。 在给定存储单元的数据被提供给数据输出缓冲器的输入端之后，启用用于驱动和控制数据输出缓冲器的信号，从而可以消除数据的任何不必要的转换操作以减少半导体的电流耗散 以防止数据存取时间的恶化，以提高半导体存储芯片的产量。

    Plasma display panel
    17.
    发明授权
    Plasma display panel 失效
    等离子显示面板

    公开(公告)号：US08120252B2

    公开(公告)日：2012-02-21

    申请号：US12820989

    申请日：2010-06-22

    申请人： Sung-Hee Cho ,  Jung-Min Kim

    发明人： Sung-Hee Cho ,  Jung-Min Kim

    IPC分类号： H01J1/62

    CPC分类号： H01J11/12 ,  H01J11/36 ,  H01J11/44 ,  H01J2211/363 ,  H01J2211/442

    摘要： A plasma display panel (PDP) is disclosed. In one embodiment, the PDP includes i) a front substrate and a rear substrate spaced apart from and facing each other and ii) a barrier rib portion dividing a space between the front substrate and the rear substrate into a plurality of discharge cells, wherein the barrier rib portion comprises first barrier ribs and second barrier ribs formed on the first barrier ribs, wherein the second barrier ribs are less in width than the first barrier ribs, wherein the widths of the first and second barrier ribs are defined along a first direction substantially parallel with one of the front and rear substrates, and wherein the second barrier ribs are closer to the first substrate than the first barrier ribs. The PDP may further include i) an anti-reflection layer formed on the second barrier ribs, ii) a plurality of discharge electrodes separately disposed on the front substrate substantially in parallel with each other across the front substrate, iii) a plurality of address electrodes formed on the rear substrate to cross the discharge electrodes, iv) phosphors formed in the discharge cells and v) a discharge gas filled in the discharge cells.

    摘要翻译： 公开了一种等离子体显示面板（PDP）。 在一个实施例中，PDP包括i）前隔板和与之相对的前基板和后基板，以及ii）将前基板与后基板之间的间隔分成多个放电单元的隔壁部分，其中， 阻挡肋部分包括形成在第一阻挡肋上的第一阻挡肋和第二阻挡肋，其中第二阻挡肋的宽度小于第一阻挡肋，其中第一和第二阻挡肋的宽度基本上沿第一方向限定 平行于前基板和后基板之一，并且其中第二阻挡肋比第一阻挡肋更靠近第一基板。 PDP可以进一步包括i）形成在第二阻挡肋上的防反射层，ii）分别布置在前基板上的多个放电电极，其基本上彼此平行地穿过前基板，iii）多个寻址电极 形成在后基板上以与放电电极交叉，iv）在放电单元中形成的荧光体，和v）填充在放电单元中的放电气体。