公开(公告)号：US20070273352A1

公开(公告)日：2007-11-29

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20110176375A1

公开(公告)日：2011-07-21

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。

公开(公告)号：US20110126039A1

公开(公告)日：2011-05-26

申请号：US12950028

申请日：2010-11-19

申请人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-II Park

发明人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-II Park

IPC分类号： G06F1/06 ,  G11C7/22

CPC分类号： G11C7/225 ,  G06F1/06 ,  G11C7/02 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

摘要翻译： 一种存储器件，包括：至少一组存储器单元，其接收用于计时命令的第一时钟和用于计时数据的第二时钟，其中所述第二时钟基于第一命令而被激活，并且基于第二命令被去激活。 所述存储装置还包括时钟激活电路，所述时钟激活电路经配置以基于所述第一命令生成使能信号和基于所述第二命令的禁用信号;以及时钟发生器，被配置为在接收到所述使能时基于参考时钟生成所述第二时钟 信号。

公开(公告)号：US20080159044A1

公开(公告)日：2008-07-03

申请号：US11888468

申请日：2007-08-01

申请人： Jang-won Moon ,  Young-hyun Jun ,  Jong-hyoung Lim

发明人： Jang-won Moon ,  Young-hyun Jun ,  Jong-hyoung Lim

IPC分类号： G11C5/14

CPC分类号： G11C5/145 ,  G11C5/147

摘要： Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.

摘要翻译： 提供了可以独立地控制内部电源电压的半导体存储器件和方法。 半导体存储器件包括存储单元阵列，参考电压产生单元，内部参考电压产生单元和内部电源电压产生单元。 参考电压产生单元响应于外部电压输出参考电压。 内部参考电压产生单元将参考电压转换为多个内部参考电压，并输出多个内部参考电压。 内部电源电压生成单元将多个内部参考电压转换为多个内部电源电压，并输出多个内部电源电压。 第一内部参考电压用于产生第一内部电源电压，而第二内部参考电压用于产生第二内部电源电压。

公开(公告)号：US06654296B2

公开(公告)日：2003-11-25

申请号：US10096345

申请日：2002-03-12

申请人： Seong-jin Jang ,  Young-hyun Jun

发明人： Seong-jin Jang ,  Young-hyun Jun

IPC分类号： G11C1604

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0041 ,  H02M2001/009 ,  H02M2003/071

摘要： Devices, circuits and methods for dual voltage generation using a single charge pump. The dual voltages can be the same or different, as they are for two different components of a device. An oscillator generates an oscillating signal, and a charge pump generates a pumping voltage at a pumping node responsive to the oscillating signal. A first switching circuit is coupled to the pumping node, and outputs from the pumping voltage a first voltage to the first component. A second switching circuit is coupled to the pumping node, and outputs from the pumping voltage a second voltage to the second component. The first and second output voltages may optionally be sensed. The oscillator may be triggered and the first and second switching circuits may be controlled as needed to maintain the sensed first and second voltages at desired values and/or ranges.

摘要翻译： 使用单个电荷泵进行双电压生成的器件，电路和方法。 双电压可以相同或不同，就像设备的两个不同组件一样。 振荡器产生振荡信号，并且电荷泵响应于振荡信号在泵浦节点产生泵浦电压。 第一开关电路耦合到泵浦节点，并且从泵浦电压输出第一电压到第一组件。 第二开关电路耦合到泵浦节点，并且从泵浦电压输出第二电压到第二组件。 可以可选地感测第一和第二输出电压。 可以触发振荡器，并且可以根据需要来控制第一和第二开关电路，以将感测到的第一和第二电压保持在期望的值和/或范围。

公开(公告)号：US07639547B2

公开(公告)日：2009-12-29

申请号：US11888468

申请日：2007-08-01

申请人： Jang-won Moon ,  Young-hyun Jun ,  Jong-hyoung Lim

发明人： Jang-won Moon ,  Young-hyun Jun ,  Jong-hyoung Lim

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C5/147

摘要： Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.

摘要翻译： 提供了可以独立地控制内部电源电压的半导体存储器件和方法。 半导体存储器件包括存储单元阵列，参考电压产生单元，内部参考电压产生单元和内部电源电压产生单元。 参考电压产生单元响应于外部电压输出参考电压。 内部参考电压产生单元将参考电压转换为多个内部参考电压，并输出多个内部参考电压。 内部电源电压生成单元将多个内部参考电压转换为多个内部电源电压，并输出多个内部电源电压。 第一内部参考电压用于产生第一内部电源电压，而第二内部参考电压用于产生第二内部电源电压。

公开(公告)号：US06813204B2

公开(公告)日：2004-11-02

申请号：US10324406

申请日：2002-12-20

申请人： Chul-soo Kim ,  Young-hyun Jun ,  Jae-goo Lee

发明人： Chul-soo Kim ,  Young-hyun Jun ,  Jae-goo Lee

IPC分类号： G11C700

CPC分类号： G11C7/1084 ,  G11C7/1048

摘要： A semiconductor memory device having a circuit precharging a data line comprises a first precharge circuit, which precharges a first data line pair to a first voltage level in a precharge operation state, and a second precharge circuit, which precharges a second data line pair to a second voltage level in a precharge operation state. The semiconductor memory device comprises a data input driver, which receives data and drives the data to the first data line pair, a switch, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and a charge-sharing control circuit, which in response to the selection signal makes one line of the first data line pair and one line of the second data line pair share charge. The semiconductor memory device reduces current consumption over repeated write/precharge operations.

摘要翻译： 具有对数据线进行预充电的电路的半导体存储器件包括：第一预充电电路，其将第一数据线对预充电到预充电操作状态下的第一电压电平;以及第二预充电电路，其将第二数据线对预充电到 在预充电操作状态下的第二电压电平。 半导体存储器件包括数据输入驱动器，其接收数据并将数据驱动到第一数据线对;开关，其响应于选择信号将第一数据线对与第二数据线对连接或断开， 以及电荷共享控制电路，其响应于选择信号使得第一数据线对的一条线和第二数据线对的一条线共享电荷。 半导体存储器件通过重复的写入/预充电操作来减少电流消耗。

公开(公告)号：US08811111B2

公开(公告)日：2014-08-19

申请号：US12950028

申请日：2010-11-19

申请人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-Il Park

发明人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-Il Park

IPC分类号： G11C8/18 ,  G11C7/22

CPC分类号： G11C7/225 ,  G06F1/06 ,  G11C7/02 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

摘要翻译： 一种存储器件，包括：至少一组存储器单元，其接收用于计时命令的第一时钟和用于计时数据的第二时钟，其中所述第二时钟基于第一命令而被激活，并且基于第二命令被去激活。 所述存储装置还包括时钟激活电路，所述时钟激活电路经配置以基于所述第一命令生成使能信号和基于所述第二命令的禁用信号;以及时钟发生器，被配置为在接收到所述使能时基于参考时钟生成所述第二时钟 信号。

公开(公告)号：US08379476B2

公开(公告)日：2013-02-19

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。

公开(公告)号：US20100026373A1

公开(公告)日：2010-02-04

申请号：US12458533

申请日：2009-07-15

申请人： Joung-Yeal Kim ,  Young-hyun Jun ,  Bai-sun Kong

发明人： Joung-Yeal Kim ,  Young-hyun Jun ,  Bai-sun Kong

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.

摘要翻译： 提供一种用于进行电荷泵送的半导体器件。 半导体器件可以包括第一泵送单元，第二泵送单元和控制器。 第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。 第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。 控制器可以被配置为控制第一和第二泵送单元。 第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。 初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。 升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。 此外，传输单元可以被配置为控制升压电压的输出。