公开(公告)号：US20080168460A1

公开(公告)日：2008-07-10

申请号：US12003947

申请日：2008-01-03

Applicant: Seung-won Lee ,  Han-cheol Kim ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim ,  Jeong-joon Yoo ,  Jae-don Lee

Inventor： Seung-won Lee ,  Han-cheol Kim ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim ,  Jeong-joon Yoo ,  Jae-don Lee

IPC: G06F9/54 ,  G06F13/24 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F13/24 ,  G06F9/5016 ,  G06F2209/504 ,  Y02D10/22

Abstract: Provided is a method and apparatus for preventing a stack overflow in an embedded system. The method of preventing a stack overflow includes: reading a maximum stack usage of at least one function for executing a requested operation from maximum stack usages of functions provided from a kernel, which are stored in advance; and processing the requested operation on the basis of the read maximum stack usage of the at least one function and a size of a usable region in a stack for the requested operation. Accordingly, the stack overflow can be prevented without generating a run-time overhead.

Abstract translation: 提供了一种用于防止嵌入式系统中的堆栈溢出的方法和装置。 防止堆栈溢出的方法包括：从预先存储的从内核提供的功能的最大堆栈使用中读取用于执行所请求操作的至少一个功能的最大堆栈使用; 以及基于所述至少一个功能的读取的最大堆栈使用量和所请求操作的堆叠中的可用区域的大小来处理所请求的操作。 因此，可以防止堆栈溢出而不产生运行时间开销。

公开(公告)号：US20080168455A1

公开(公告)日：2008-07-10

申请号：US12002758

申请日：2007-12-19

Applicant: Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

Inventor： Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

IPC: G06F9/46

CPC classification number: G06F9/4887

Abstract: A scheduling method, medium and apparatus are provided. In the scheduling method, medium and apparatus, it is possible to prevent the possibility that the order between the priorities of the tasks represented by the expired timers and the tasks requested by the interrupt is reversed while also not deteriorating the performance of a real time operating system (RTOS), even though the number of timers expired when the interrupt occurs or that are already expired before the interrupt occurs is large, by selecting a timer for representing a point of time corresponding to a point of time when an interrupt occurs from among one or more timers each of which representing a task, a point of time assigned to the tasks, and a priority assigned to the task and executing a task represented by the selected timer and one or more tasks requested by the interrupt in order of priority.

Abstract translation: 提供了调度方法，介质和设备。 在调度方法，媒体和装置中，可以防止由过期定时器表示的任务的优先级与中断所请求的任务之间的顺序相反的可能性，同时也不会恶化实时操作的性能 系统（RTOS），即使当中断发生时或者已经在中断发生之前已经到期的定时器数量过大时，通过选择用于表示与从中间发生的时间点相对应的时间点的定时器， 表示任务的一个或多个定时器，分配给任务的时间点，以及分配给该任务的优先级，并且以优先级顺序执行由所选定时器所表示的任务和中断所请求的一个或多个任务。

公开(公告)号：US08194658B2

公开(公告)日：2012-06-05

申请号：US11979737

申请日：2007-11-07

Applicant: Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jeong-joon Yoo ,  Jae-don Lee ,  Min-kyu Jeong ,  Keun-soo Yim

Inventor： Young-sam Shin ,  Seung-won Lee ,  Han-cheol Kim ,  Jeong-joon Yoo ,  Jae-don Lee ,  Min-kyu Jeong ,  Keun-soo Yim

IPC: H04L12/56

CPC classification number: H04L47/564 ,  H04L47/19 ,  H04L47/24 ,  H04L47/50

Abstract: A method and apparatus transmitting and receiving in a real-time system are disclosed. The method of transmitting in a real-time system includes scheduling a task included in a socket based on a predetermined transmission option designated to the socket, and transmitting a packet generated by the scheduled task based on the predetermined transmission option, so that real-time communications of a network communication can be secured and resources of the system can be efficiently used, thereby, transmitting and receiving data according to the required characteristics of transmission and reception.

Abstract translation: 公开了一种在实时系统中发送和接收的方法和装置。 在实时系统中发送的方法包括基于指定给套接字的预定传输选项来调度包含在套接字中的任务，以及基于预定传输选项发送由调度任务生成的分组，使得实时 可以确保网络通信的通信，并且可以有效地利用系统的资源，从而根据所需的发送和接收特性发送和接收数据。

公开(公告)号：US08171267B2

公开(公告)日：2012-05-01

申请号：US12216149

申请日：2008-06-30

Applicant: Seung-won Lee

Inventor： Seung-won Lee

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different data to process in response to the instruction from the first process, the instruction being to execute the task; selecting a method of migrating the first process or a method of migrating a thread included in the first process based on the examining and migrating the task from a first processor to the second processor using the selected method. Therefore, cost and power required for task migration can be minimized. Consequently, power consumption can be maintained in a low-power environment, such as an embedded system, which, in turn, optimizes the performance of the multi-processor system and prevents physical damage to the circuit of the multi-processor system.

Abstract translation: 一种用于在多处理器系统中迁移任务的方法和装置。 该方法包括检查第二处理是否已被分配给第二处理器，第二处理具有作为第一处理执行的相同指令，并且具有响应于来自第一处理的指令而处理的不同数据，该指令将执行 任务; 基于使用所选择的方法从第一处理器检查和迁移任务到第二处理器，选择迁移第一进程的方法或迁移包括在第一进程中的线程的方法。 因此，任务迁移所需的成本和功耗可以最小化。 因此，能够在诸如嵌入式系统的低功率环境中维持功率消耗，这进而优化多处理器系统的性能并防止对多处理器系统的电路的物理损坏。

公开(公告)号：US20090187912A1

公开(公告)日：2009-07-23

申请号：US12216149

申请日：2008-06-30

Applicant: Seung-won Lee

Inventor： Seung-won Lee

IPC: G06F9/46

CPC classification number: G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different data to process in response to the instruction from the first process, the instruction being to execute the task; selecting a method of migrating the first process or a method of migrating a thread included in the first process based on the examining and migrating the task from a first processor to the second processor using the selected method. Therefore, cost and power required for task migration can be minimized. Consequently, power consumption can be maintained in a low-power environment, such as an embedded system, which, in turn, optimizes the performance of the multi-processor system and prevents physical damage to the circuit of the multi-processor system.

Abstract translation: 一种用于在多处理器系统中迁移任务的方法和装置。 该方法包括检查第二处理是否已被分配给第二处理器，第二处理具有作为第一处理执行的相同指令，并且具有响应于来自第一处理的指令而处理的不同数据，该指令将执行 任务; 基于使用所选择的方法从第一处理器检查和迁移任务到第二处理器，选择迁移第一进程的方法或迁移包括在第一进程中的线程的方法。 因此，任务迁移所需的成本和功耗可以最小化。 因此，能够在诸如嵌入式系统的低功率环境中维持功率消耗，这进而优化多处理器系统的性能并防止对多处理器系统的电路的物理损坏。

公开(公告)号：US20080195916A1

公开(公告)日：2008-08-14

申请号：US12010244

申请日：2008-01-23

Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G11C29/00

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

公开(公告)号：US20080168210A1

公开(公告)日：2008-07-10

申请号：US12004068

申请日：2007-12-20

Applicant: Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

Inventor： Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

IPC: G06F12/00

CPC classification number: G06F11/1008

Abstract: A method and apparatus for managing a memory are provided. It is possible to rapidly recover the area allocated or desired to be returned by easily recognizing a range of the area allocated or desired to be returned over the entire area of the memory by recognizing an original area of a predetermined memory chunk interrupted by a neighboring memory chunk among a series of memory chunks that make up the memory by considering an original area of the neighboring memory chunk and by recovering the predetermined memory chunk and the recognized area to their original areas, when the area allocated to or returned by an application program is interrupted.

Abstract translation: 提供了一种用于管理存储器的方法和装置。 通过识别由相邻存储器中断的预定存储器块的原始区域，可以容易地识别在存储器的整个区域中分配或期望返回的区域的范围，来快速恢复分配或期望返回的区域 在通过考虑相邻存储块的原始区域构成存储器的一系列存储块中的块，并且通过将分配给应用程序或由应用程序返回的区域归为原始区域时将预定的存储块和识别的区域恢复到其原始区域 中断了

公开(公告)号：US07098018B2

公开(公告)日：2006-08-29

申请号：US10481531

申请日：2002-07-06

Applicant: Young-Phil Lee ,  Seung-won Lee ,  Chul-ho Jung ,  Hyung-Cheol Kim ,  Soon-Yong Choi ,  Jin-suk Kim ,  Hyun-Sik Kim ,  Jung-Woo Seo

Inventor： Young-Phil Lee ,  Seung-won Lee ,  Chul-ho Jung ,  Hyung-Cheol Kim ,  Soon-Yong Choi ,  Jin-suk Kim ,  Hyun-Sik Kim ,  Jung-Woo Seo

IPC: C12N9/56 ,  C12N15/57 ,  C12N15/74 ,  C12P21/06

CPC classification number: C12N9/54

Abstract: The present invention relates to novel aminopeptidase derived from Bacillus licheniformis, a gene encoding the aminopeptidase, an expression vector containing the gene, a cell transformant transfected with the expression vector and a process for preparing a natural type protein using thereof. More particularly, the present invention relates to a gene encoding aminopeptidase which is cloned and manufactured using the recombinant DNA technique, an expression vector containing the gene, a cell transformant transfected with the expression vector and a recombinant aminopeptidase which is necessary to produce recombinant human growth hormone in a natural type protein and can be expressed in a high yield more stably and advantageously, compared with conventional methods for the purification.

Abstract translation: 本发明涉及来源于地衣芽孢杆菌的新氨基肽酶，编码氨基肽酶的基因，含有该基因的表达载体，用表达载体转染的细胞转化体和使用其制备天然型蛋白质的方法。 更具体地，本发明涉及使用重组DNA技术克隆和制造的氨基肽酶的基因，含有该基因的表达载体，用表达载体转染的细胞转化体和产生重组人生长所必需的重组氨基肽酶 与常规的纯化方法相比，可以更稳定和有利地以高产率表达天然型蛋白质中的激素。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US08659394B2

公开(公告)日：2014-02-25

申请号：US13093254

申请日：2011-04-25

Applicant: Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

Inventor： Il-jong Song ,  Byeong-hoon Lee ,  Seung-won Lee ,  Chul-joon Choi

IPC: H04Q5/22 ,  H04L5/12 ,  H03D3/02

CPC classification number: G06K19/07771 ,  H04Q2213/095

Abstract: Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.

Abstract translation: 提供了具有信号接收方法的射频识别（RFID）标签。 RFID标签包括接收包含读取数据的读取信号的解调器。 解调器包括： 电压产生电路，其提供从所接收的读取信号导出的第一电压信号和第二电压信号;反相器，其通过使用相对于所述读取信号定义的反相电压来反转所述第二电压信号来提供指示所述读取数据的数据脉冲信号 第一电压信号和通过缓冲数据脉冲信号来恢复读取数据的缓冲器。