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    Method and a system for a quick verification rabin signature scheme
    11.
    发明授权
    Method and a system for a quick verification rabin signature scheme 失效
    用于快速验证rabin签名方案的方法和系统

    公开(公告)号：US07760873B2

    公开(公告)日：2010-07-20

    申请号：US11479100

    申请日：2006-06-30

    申请人： Shay Gueron ,  Vinodh Gopal

    发明人： Shay Gueron ,  Vinodh Gopal

    IPC分类号： H04L9/30

    CPC分类号： H04L9/302 ,  H04L9/3249

    摘要： A method and a system to perform a Quick Verification of a Rabin Signature (QVRS) is provided. In one embodiment, the signing party generates a Rabin signature S of an original message M using a public key N in the Rabin signature generating formula M=S2 mod N. In one embodiment, the signing party also generates a value q according to the formula q=floor(S2/N). In one embodiment, the signing party sends the original message M, the signature S, the public key N and the value q to the verifying party. In one embodiment, the verifying party verifies the integrity of the message M using the signature S, the public key N and the value q and the test equation M=S2−qN.

    摘要翻译： 提供了一种执行拉宾签名快速验证（QVRS）的方法和系统。 在一个实施例中，签名方使用Rabin签名生成公式M = S2 mod N中的公共密钥N来生成原始消息M的Rabin签名S.在一个实施例中，签约方还根据公式生成值q q = floor（S2 / N）。 在一个实施例中，签名方向验证方发送原始消息M，签名S，公钥N和值q。 在一个实施例中，验证方使用签名S，公钥N和值q以及测试方程M = S2-qN验证消息M的完整性。

    Determining a message residue
    13.
    发明授权
    Determining a message residue 有权
    确定消息残差

    公开(公告)号：US08689078B2

    公开(公告)日：2014-04-01

    申请号：US11777538

    申请日：2007-07-13

    申请人： Shay Gueron ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Gilbert M. Wolrich

    发明人： Shay Gueron ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Gilbert M. Wolrich

    IPC分类号： H03M13/00

    CPC分类号： H03M13/091

    摘要： A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

    摘要翻译： 确定消息残差的技术包括访问消息并且同时确定关于消息的不同相应段的多项式的一组模块余数。 该技术还包括基于模块余数的集合和在访问消息之前确定的一组常数来确定关于消息的多项式的模块余数。 相对于消息的多项式的模数余数存储在存储器中。

    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES)
    16.
    发明申请
    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 有权
    实施高级加密标准（AES）的架构和指导

    公开(公告)号：US20120002804A1

    公开(公告)日：2012-01-05

    申请号：US13088088

    申请日：2011-04-15

    申请人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    发明人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

    摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    摘要翻译： 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCESSING
    19.
    发明申请
    INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCESSING 审中-公开

    公开(公告)号：US20180260218A1

    公开(公告)日：2018-09-13

    申请号：US15452150

    申请日：2017-03-07

    申请人： Vinodh Gopal

    发明人： Vinodh Gopal

    IPC分类号： G06F9/26 ,  G06F9/30 ,  G06F9/345

    CPC分类号： G06F9/44547 ,  G06F1/3203 ,  G06F1/3287 ,  G06F8/447 ,  G06F8/47 ,  G06F9/268 ,  G06F9/30061 ,  G06F9/345 ,  G06F9/3557 ,  G06F9/3877 ,  G06F9/44521 ,  G06F9/5066 ,  G06F15/76

    摘要： Instruction set architectures (ISA) for fine-grained heterogeneous processing and associated processors, methods, and compilers. The ISA includes instructions that are configured to be executed on processors having heterogeneous cores implementing different micro-architectures. Mechanisms are provided to enable respective code segments to be compiled/assembled for a target processor (or processor family) with heterogeneous cores and have appropriate code segments that has been compiled for specific types of processor core micro-architectures be dynamically called at run-time via execution of the ISA instructions. The ISA instructions include both unconditional and conditional branch and call instructions, in addition to instructions that support processors with three or more different types of cores. The instructions are configured to support dynamic migration of instruction threads across heterogeneous cores while adding substantially no overhead. A compiler is also provided to generate and assemble opcode segments configured to be executed on processors with heterogeneous cores.

    INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING
    20.
    发明申请
    INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING 审中-公开

    公开(公告)号：US20180095760A1

    公开(公告)日：2018-04-05

    申请号：US15281380

    申请日：2016-09-30

    申请人： James D. Guilford ,  Vinodh Gopal

    发明人： James D. Guilford ,  Vinodh Gopal

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30192

    摘要： Instruction sets for variable length integer (varint) coding and associated methods and apparatus. The instructions sets include instructions for encoding and decoding varints, and may be included as a part of an instruction set architecture (ISA) for processors architectures such as x86 and Arm-based architectures, as well as other ISAs. In one aspect, the instructions include, a varint size encode instruction to encode a size of a varint, a varint encode instruction to encode a varint, a varint size decode instruction to decode a size of an encoded varint, and a varint decode instruction to decode an encoded varint. Varint encode size and encode instructions may be combined in a single instructions. Similarly, varint decode size and decode instructions may be combined in a single instruction. In one aspect, the instructions use a variable-length quantity (VLQ) encoding scheme under which varints are encoded into one or more VLQ octets.