公开(公告)号：US08880382B2

公开(公告)日：2014-11-04

申请号：US13352713

申请日：2012-01-18

申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

IPC分类号： G06G7/48

CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

公开(公告)号：US20110173577A1

公开(公告)日：2011-07-14

申请号：US12024390

申请日：2008-02-01

申请人： Ching-Te K. Chuang ,  Fook-Luen Heng ,  Rouwaida Kanj ,  Keunwoo Kim ,  Jin-Fuw Lee ,  Saibal Mukhopadhyay ,  Sani Richard Nassif ,  Rama Nand Singh

发明人： Ching-Te K. Chuang ,  Fook-Luen Heng ,  Rouwaida Kanj ,  Keunwoo Kim ,  Jin-Fuw Lee ,  Saibal Mukhopadhyay ,  Sani Richard Nassif ,  Rama Nand Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.

摘要翻译： 提供了改进电路设计和生产的技术。 一方面，提供了一种用于虚拟制造过程敏感电路的方法。 该方法包括以下步骤。 基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。 基于质量的度量用于为制造的电路的虚拟表示投影产量。 物理布局图和/或生产过程被修改。 重复获得，使用和修改步骤，直到达到期望的预计产量。

公开(公告)号：US07508697B1

公开(公告)日：2009-03-24

申请号：US11746448

申请日：2007-05-09

申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Keejong Kim ,  Kaushik Roy

发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Keejong Kim ,  Kaushik Roy

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/02 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/5006

摘要： A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die Vt process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die Vt process corner, thereby reducing possible access and write failures.

摘要翻译： 一种自修复SRAM和一种减少SRAM中参数故障的方法。 采用片内泄漏或延迟监测器来检测晶片间Vt过程角，响应于此，SRAM应用自适应体偏置以减少管芯中参数故障的数量并提高记忆产量。 实施例包括用于在存在低的晶片间Vt处理角的情况下将反向偏置（RBB）施加到SRAM阵列的电路，从而减少可能的读取和保持故障，并且在存在时向阵列应用前向偏置（FBB） 的高间隔Vt处理角，从而减少可能的访问和写入失败。

公开(公告)号：US08682634B2

公开(公告)日：2014-03-25

申请号：US13613061

申请日：2012-09-13

申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E Rosenbluth ,  Rama N. Singh ,  Kehan Tian

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

公开(公告)号：US08086917B2

公开(公告)日：2011-12-27

申请号：US12542187

申请日：2009-08-17

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

摘要翻译： 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US20090091346A1

公开(公告)日：2009-04-09

申请号：US11866502

申请日：2007-10-03

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Saibal Mukhopadhyay

IPC分类号： G01R31/26

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/12005 ,  G11C2029/5002

摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.

摘要翻译： 电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压 第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。 多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。 解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。 电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差 在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

公开(公告)号：US20130185046A1

公开(公告)日：2013-07-18

申请号：US13613061

申请日：2012-09-13

申请人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

发明人： Saeed Bagheri ,  Fook-Luen Heng ,  Rajiv Vasant Joshi ,  Kafai Lai ,  David Osmond Melville ,  Saibal Mukhopadhyay ,  Alan E. Rosenbluth ,  Rama N. Singh ,  Kehan Tian

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F2217/10

摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

公开(公告)号：US07642864B2

公开(公告)日：2010-01-05

申请号：US12021459

申请日：2008-01-29

申请人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

发明人： Ching-Te K. Chuang ,  Jae-Joon Kim ,  Tae-Hyoung Kim ,  Pong-Fei Lu ,  Saibal Mukhopadhyay ,  Rahul M. Rao ,  Shao-yi Wang

IPC分类号： G01R23/00 ,  G01R27/00 ,  G01R27/28 ,  H03B5/24 ,  H03K3/03

CPC分类号： H03K3/0315

摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

摘要翻译： 环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。 所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。 在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。 在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。 还包括类似的基于NAND门的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路 通过门。

公开(公告)号：US07304903B2

公开(公告)日：2007-12-04

申请号：US11337348

申请日：2006-01-23

申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C11/413

摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

摘要翻译： 读出放大器电路包括具有限定到电路的第一输入的第一栅极的第一双栅极金属氧化物半导体场效应晶体管（DGMOSFET），耦合到该电路的第一输出的第二栅极和输出端以及第二DGMOSFET 具有限定电路的第二输入的第一栅极，连接到第一DGMOSFET的输出的第二栅极和连接到第一DGMOSFET的第二栅极的输出端，第二DGMOSFET的输出耦合到第二DGMOSFET的第二输出端 电路。

公开(公告)号：US20060220679A1

公开(公告)日：2006-10-05

申请号：US11099386

申请日：2005-04-05

申请人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

发明人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

IPC分类号： H03K19/173

CPC分类号： G01R31/31858

摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。