公开(公告)号：US20130334671A1

公开(公告)日：2013-12-19

申请号：US13613309

申请日：2012-09-13

Applicant: Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

Inventor： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

IPC: H01L23/495

CPC classification number: H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

Abstract translation: 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

公开(公告)号：US20130249070A1

公开(公告)日：2013-09-26

申请号：US13426804

申请日：2012-03-22

Applicant: Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

Abstract: A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

Abstract translation: 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

公开(公告)号：US20130234094A1

公开(公告)日：2013-09-12

申请号：US13416183

申请日：2012-03-09

Applicant: Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

Abstract translation: 公开了一种用于电阻随机存取存储器（RRAM）装置的方法和装置。 RRAM器件包括底电极，设置在底电极上的电阻开关层和设置在电阻开关层上的顶电极。 电阻开关层由金属，Si和O的复合材料制成。在顶部电极和底部电极之间可能存在额外的隧道势垒层。 顶部电极和底部电极可以包括多个子层。

公开(公告)号：US08099861B2

公开(公告)日：2012-01-24

申请号：US12854214

申请日：2010-08-11

Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

IPC: B23P19/02 ,  B23P19/04 ,  B23P19/10 ,  B23P19/12 ,  C25D17/12 ,  C25D17/14 ,  C25D3/38

CPC classification number: H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

Abstract translation: 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

公开(公告)号：US20100314256A1

公开(公告)日：2010-12-16

申请号：US12854214

申请日：2010-08-11

Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

IPC: C25D5/00 ,  H01R43/00 ,  C25F3/16 ,  C25F3/22

CPC classification number: H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

Abstract translation: 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

公开(公告)号：US07737056B2

公开(公告)日：2010-06-15

申请号：US11682137

申请日：2007-03-05

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: D03D9/00 ,  B32B5/26

CPC classification number: B32B5/26 ,  D04H1/4374 ,  Y10T442/10 ,  Y10T442/107 ,  Y10T442/153 ,  Y10T442/183

Abstract: A moisture-wicking and fast drying cloth has an outer layer and an inner layer. The outer layer is made of hydrophilic synthetic fiber and has multiple meshes. The meshes are defined through the outer layer. The inner layer is made of hydrophobic synthetic fiber and is bonded to the outer layer. The inner layer exposed by the meshes pulls away from a person's skin and protrudes into the meshes when perspiration exceeds evaporating moisture from the outer layer, so area of the inner layer contacting the person's skin will be reduced to make the person comfortable.

Abstract translation: 吸湿排汗快干布具有外层和内层。 外层由亲水性合成纤维制成，具有多个网眼。 网格是通过外层定义的。 内层由疏水性合成纤维制成，并与外层结合。 网眼暴露的内层从人体的皮肤拉开，突出于网眼，当汗水超出外层蒸发水分时，内层与人体皮肤接触的面积减小，使人感到舒适。

公开(公告)号：US20080222350A1

公开(公告)日：2008-09-11

申请号：US12073506

申请日：2008-03-06

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: G06F12/00

CPC classification number: G06F12/0246

Abstract: A flash memory device which comprises a controller and one or plurality of flash memories for storing data and method thereof are disclosed. The controller comprises a control interface to accept data access which is from a main board and is managed by a control element of flash memory and a buffer management element. Through a micro-processing element in the controller, the data access from main board is checked for a random access or a serial page access. The random access and serial page access are written to different blocks by different processes in one or plurality of flash memories. The lifetime and processing speed of flash memories are improved for reduced erasure times during writing data.

Abstract translation: 公开了一种包括控制器和用于存储数据的一个或多个闪速存储器及其方法的闪速存储器件。 控制器包括一个控制接口，用于接受来自主板的数据访问，并由闪存的控制元件和缓冲器管理元件进行管理。 通过控制器中的微处理元件，对主板的数据访问进行随机访问或串行页访问。 随机访问和串行页面访问通过一个或多个闪存中的不同进程写入不同的块。 提高闪存的寿命和处理速度，以减少写入数据时的擦除时间。

公开(公告)号：US07278751B2

公开(公告)日：2007-10-09

申请号：US11174868

申请日：2005-07-05

Applicant: Shih-Chieh Chang ,  Juan-Hsin Lu

Inventor： Shih-Chieh Chang ,  Juan-Hsin Lu

IPC: B25B23/18

CPC classification number: B25B23/18 ,  B25B15/02

Abstract: A screwdriver includes a handle including a receptacle for coupling with an end of a bit. A front groove and a rear groove are respectively defined in a front end and a rear end of the handle. A plurality of light-emitting diodes are mounted on a circuit board in the front groove of the handle. A transparent cover is mounted in the front groove and in front of the light-emitting diodes. A front cap is mounted to the front end of the handle. A cell and a switch are mounted in the rear groove. A rear cap is mounted to the rear end of the handle. The switch, the cell, the circuit board, and the light-emitting diodes are electrically connected. The light-emitting diodes forwardly emit light beams passing through the transparent cover to provide illumination when required.

Abstract translation: 螺丝刀包括一把手，该把手包括用于与一位的端部连接的插座。 前槽和后槽分别限定在手柄的前端和后端。 多个发光二极管安装在手柄的前槽中的电路板上。 透明盖安装在前槽和发光二极管的前面。 前盖安装到手柄的前端。 电池和开关安装在后槽中。 后盖安装到手柄的后端。 开关，电池，电路板和发光二极管电连接。 发光二极管向前发射穿过透明盖的光束，以在需要时提供照明。

公开(公告)号：US07224178B2

公开(公告)日：2007-05-29

申请号：US11014170

申请日：2004-12-17

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: H03K19/003

CPC classification number: H03K19/00323

Abstract: By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.

Abstract translation: 通过将冗余逻辑门添加到电路中而不改变整个电路的功能，本发明可以容忍某些延迟变化。 本发明可以应用于IC行业以提高半导体制造的产量。

公开(公告)号：US20060132169A1

公开(公告)日：2006-06-22

申请号：US11014170

申请日：2004-12-17

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: H03K19/003

CPC classification number: H03K19/00323

Abstract: By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.

Abstract translation: 通过将冗余逻辑门添加到电路中而不改变整个电路的功能，本发明可以容忍某些延迟变化。 本发明可以应用于IC行业以提高半导体制造的产量。