公开(公告)号：US08704345B2

公开(公告)日：2014-04-22

申请号：US13613309

申请日：2012-09-13

申请人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

发明人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

摘要翻译： 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

公开(公告)号：US20130334681A1

公开(公告)日：2013-12-19

申请号：US13525460

申请日：2012-06-18

申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

摘要翻译： 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US08658466B2

公开(公告)日：2014-02-25

申请号：US13525460

申请日：2012-06-18

申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Lung-Hua Ho ,  Chaun-Yu Wu ,  Kung-An Lin

IPC分类号： H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.

摘要翻译： 半导体封装结构包括第一衬底，第二衬底和密封剂。 第一基板包括多个第一凸块和多个第一焊料层。 每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。 第二基板包括多个第二凸块和多个第二焊料层。 每个第二焊料层形成在每个第二凸块上并且包括外表面。 每个第二焊料层是锥形体。 第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。 锥形槽的内表面与第二焊料层的外表面接触。 密封剂形成在第一基板和第二基板之间。

公开(公告)号：US08581384B2

公开(公告)日：2013-11-12

申请号：US13426804

申请日：2012-03-22

申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

IPC分类号： H01L23/48

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

公开(公告)号：US20130334671A1

公开(公告)日：2013-12-19

申请号：US13613309

申请日：2012-09-13

申请人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

发明人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

IPC分类号： H01L23/495

CPC分类号： H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

摘要翻译： 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

公开(公告)号：US20130249070A1

公开(公告)日：2013-09-26

申请号：US13426804

申请日：2012-03-22

申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

公开(公告)号：US20140035125A1

公开(公告)日：2014-02-06

申请号：US13562551

申请日：2012-07-31

申请人： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hiu Chen

发明人： Chih-Ming Kuo ,  Lung-Hua Ho ,  Kung-An Lin ,  Sheng-Hiu Chen

IPC分类号： H01L21/60 ,  H01L23/498

CPC分类号： H01L21/76885 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16058 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A semiconductor manufacturing method includes providing a carrier having a metallic layer, wherein the metallic layer comprises a plurality of base areas and a plurality of outer lateral areas; forming a first photoresist layer; forming a plurality of bearing portions; removing the first photoresist layer to reveal the bearing portions, each bearing portion comprises a bearing surface having a first area and a second area; forming a second photoresist layer for revealing the first areas of the bearing surfaces; forming a plurality of connection portions, wherein the first areas of the bearing surfaces are covered by the connection portions to make each connection portion connect with each bearing portion to form a snap bump; removing the outer lateral areas of the metallic layer to make the base areas form a plurality of under bump metallurgy layers.

公开(公告)号：US20120211257A1

公开(公告)日：2012-08-23

申请号：US13030203

申请日：2011-02-18

申请人： Chih-Hung Wu ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Cheng-Hung Shih ,  Yie-Chuan Chiu

发明人： Chih-Hung Wu ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Cheng-Hung Shih ,  Yie-Chuan Chiu

IPC分类号： H01B7/00

CPC分类号： H01L23/49811 ,  H01L23/295 ,  H01L2224/10126 ,  H01L2224/13565 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process.

摘要翻译： 用于电耦合到载体上的接合焊盘的金字塔凸块结构包括设置在接合焊盘处的导电块和在导电块的一侧被覆盖的斜锥形绝缘层。 倾斜金字塔绝缘层包括底部和顶部，倾斜金字塔绝缘层的外径从底部到顶部逐渐变细。 当载体与衬底连接并且设置在衬底上的各向异性导电膜时，金字塔凸块结构可以快速地嵌入到各向异性导电膜中以提高各向异性导电膜的流速。 此外，可以避免相邻凸点之间的短暂现象，以提高封装处理的成品率。

公开(公告)号：US08692390B2

公开(公告)日：2014-04-08

申请号：US13030203

申请日：2011-02-18

申请人： Chih-Hung Wu ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Cheng-Hung Shih ,  Yie-Chuan Chiu

发明人： Chih-Hung Wu ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Cheng-Hung Shih ,  Yie-Chuan Chiu

IPC分类号： H01L29/40

CPC分类号： H01L23/49811 ,  H01L23/295 ,  H01L2224/10126 ,  H01L2224/13565 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A pyramid bump structure for electrically coupling to a bond pad on a carrier comprises a conductive block disposed at the bond pad and an oblique pyramid insulation layer covered at one side of the conductive block. The oblique pyramid insulation layer comprises a bottom portion and a top portion, and outer diameter of the oblique pyramid insulation layer is tapered from the bottom portion to the top portion. When the carrier is connected with a substrate and an anisotropic conductive film disposed at the substrate, the pyramid bump structure may rapidly embed into the anisotropic conductive film to raise the flow rate of the anisotropic conductive film. Further, a short phenomenon between adjacent bumps can be avoided to raise the yield rate of package process.

摘要翻译： 用于电耦合到载体上的接合焊盘的金字塔凸块结构包括设置在接合焊盘处的导电块和在导电块的一侧被覆盖的斜锥形绝缘层。 倾斜金字塔绝缘层包括底部和顶部，倾斜金字塔绝缘层的外径从底部到顶部逐渐变细。 当载体与衬底连接并且设置在衬底上的各向异性导电膜时，金字塔凸块结构可以快速地嵌入到各向异性导电膜中以提高各向异性导电膜的流速。 此外，可以避免相邻凸点之间的短暂现象，以提高封装处理的成品率。

公开(公告)号：US08415243B1

公开(公告)日：2013-04-09

申请号：US13352530

申请日：2012-01-18

申请人： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

发明人： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

IPC分类号： H01L21/44

CPC分类号： H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11472 ,  H01L2224/1182 ,  H01L2224/11906 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/05552

摘要： A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.

摘要翻译： 凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层 金属层，图案化光致抗蚀剂层以形成多个开口槽，在开口槽处形成多个底部覆盖层，进行热过程，形成多个外部覆盖层，以使每个外部覆盖层与每个 的底部覆盖层，其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块，在外部覆盖层上形成多个连接层，去除光致抗蚀剂层，去除第二区域并使能 每个第一区域形成凸块下的冶金层。