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141 条记录 (耗时 0.032 秒)

    Electrostatic discharge device control and structure
    12.
    发明授权
    Electrostatic discharge device control and structure 失效
    静电放电装置的控制和结构

    公开(公告)号：US08514535B2

    公开(公告)日：2013-08-20

    申请号：US12987276

    申请日：2011-01-10

    申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

    发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0285

    摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.

    摘要翻译： 提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/​​输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。 第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。 第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures
    13.
    发明授权
    Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权
    用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法

    公开(公告)号：US08503140B2

    公开(公告)日：2013-08-06

    申请号：US12898013

    申请日：2010-10-05

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

    摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

    摘要翻译： 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

    Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures
    14.
    发明授权
    Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures 有权
    具有用于增强静电放电保护的体对衬底连接的绝缘体上半导体器件结构以及这种绝缘体上半导体器件结构的设计结构

    公开(公告)号：US08217455B2

    公开(公告)日：2012-07-10

    申请号：US12102032

    申请日：2008-04-14

    申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L27/0248

    摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

    摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

    Substrate triggering for ESD protection in SOI
    17.
    发明授权
    Substrate triggering for ESD protection in SOI 有权
    SOI中ESD保护的衬底触发

    公开(公告)号：US07746607B2

    公开(公告)日：2010-06-29

    申请号：US11380525

    申请日：2006-04-27

    申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0266

    摘要： Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.

    摘要翻译： 静电放电（ESD）保护装置和保护常规FET的工艺。 该器件包括至少一个形成电阻的FET体，以及耦合到保护FET和电阻的触发电路。 电阻提高至少一个体的电压，使得保护FET在比常规FET低的电压下被触发。

    Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
    18.
    发明授权
    Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers 有权
    用于动态偏置的结构和方法，以改善电流模式逻辑（CML）驱动器的ESD稳健性

    公开(公告)号：US09219055B2

    公开(公告)日：2015-12-22

    申请号：US13517849

    申请日：2012-06-14

    申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan D. Jack ,  Jun Jun Li ,  Souvick Mitra

    发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Nathan D. Jack ,  Jun Jun Li ,  Souvick Mitra

    IPC分类号： H03K19/086 ,  H03K19/0175 ,  H01L27/02

    CPC分类号： H02H9/005 ,  G06F17/5081 ,  H01L27/0251 ,  H01L27/0281 ,  H01L27/0285 ,  H02H9/04 ,  H02H9/046 ,  H03K17/687

    摘要： An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

    摘要翻译： 具有CML驱动器的集成电路，其包括驱动器偏置网络。 第一输出焊盘和第二输出焊盘连接到电压焊盘。 第一驱动器连接到第一输出焊盘和电压焊盘。 第二驱动器连接到第二输出焊盘和电压焊盘。 第一ESD电路连接到电压焊盘，第一输出焊盘和第一驱动器。 第二ESD电路连接到电压焊盘，第二输出焊盘和第二驱动器。 当在第一输出焊盘处发生ESD事件时，第一ESD电路将第一驱动器偏压到电压焊盘的电压，并且当在第二ESD处发生ESD事件时，第二ESD电路将第二驱动器偏压到电压焊盘的电压 输出板。

    Vertical current controlled silicon on insulator (SOI) device such as a silicon controlled rectifier and method of forming vertical SOI current controlled devices
    19.
    发明授权
    Vertical current controlled silicon on insulator (SOI) device such as a silicon controlled rectifier and method of forming vertical SOI current controlled devices 有权
    垂直电流控制绝缘体上硅（SOI）器件，例如可控硅整流器，以及形成垂直SOI电流控制器件的方法

    公开(公告)号：US08815654B2

    公开(公告)日：2014-08-26

    申请号：US11762811

    申请日：2007-06-14

    申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A Mousa ,  Christopher S. Putnam

    发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A Mousa ,  Christopher S. Putnam

    IPC分类号： H01L21/84 ,  H01L27/02

    CPC分类号： H01L27/0262

    摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

    摘要翻译： 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。