公开(公告)号：US08476760B2

公开(公告)日：2013-07-02

申请号：US13288161

申请日：2011-11-03

申请人： Manoj K. Jain ,  Sreenivasan Koduri

发明人： Manoj K. Jain ,  Sreenivasan Koduri

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.

摘要翻译： 集成电路上的接合焊盘设置有平坦化电介质结构，以允许具有平坦顶表面的金属柱的电镀。 金属柱与平坦化电介质结构的至少三面接触。 平面化电介质结构可以用于具有不同尺寸的接合焊盘的集成电路以电镀具有相同高度的金属柱。

公开(公告)号：US20060237828A1

公开(公告)日：2006-10-26

申请号：US11112336

申请日：2005-04-22

申请人： William Robinson ,  Sreenivasan Koduri

发明人： William Robinson ,  Sreenivasan Koduri

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00

摘要： System and method for enhancing the performance of wafer chip scale packages (WCSP). A preferred embodiment comprises a parent electrical device 305 and a daughter electrical device 310 coupled to a bottom surface of the parent electrical device, wherein the bottom surface is also used to attach the parent electrical device to a circuit board. A passivation layer is formed over the daughter electrical device to protect it from environmental dangers. The passivation layer also prevents the detachment of the daughter electrical device when the parent electrical device is attached to the circuit board. Solder bumps attached to the parent electrical device permit the attachment of the parent electrical device to the circuit board. The inclusion of the daughter electrical device can add desired functionality as well as permit the use of optimized fabrication processes for different types of integrated circuitry.

摘要翻译： 用于提高晶片尺寸封装（WCSP）性能的系统和方法。 优选实施例包括母电装置305和耦合到母电装置的底表面的子电装置310，其中底表面也用于将母电装置附接到电路板。 在子电气设备上形成钝化层以保护其免受环境危害。 当母电装置附接到电路板时，钝化层还防止子电装置的分离。 连接到母电气设备的焊接凸起允许母电气设备连接到电路板。 包含子电子装置可以增加所需的功能，并且允许对不同类型的集成电路使用优化的制造工艺。

公开(公告)号：US20060217817A1

公开(公告)日：2006-09-28

申请号：US11423880

申请日：2006-06-13

申请人： David Bon ,  Sreenivasan Koduri

发明人： David Bon ,  Sreenivasan Koduri

IPC分类号： G05B19/18

CPC分类号： G05B19/4083 ,  G05B2219/36046 ,  G05B2219/36048 ,  G05B2219/45033

摘要： A computerized system and method for customizing bond programs in order to compensate first for variabilities in an integrated circuit (IC) “slave” bonder, and second to any irregularities in a “slave” circuit positioned on the slave bonder for attaching connecting bonds onto the IC bond pads. According to the invention, a “master” segmentator groups the bond pads of a “master” circuit on a master bonder into segments and stores the reference data related to these segments in a master file. Next, a slave regenerator, coupled to the master file, regenerates the master reference data so that variable characteristics of the slave bonder are defined and adaptively compensated. Finally, a slave corrector, coupled to the salve regenerator, corrects the bond program for the slave circuit on the adaptively compensated slave bonder. The slave bonder attaches the connecting bonds based on the computed correct bond locations.

摘要翻译： 一种用于定制键合程序的计算机化系统和方法，以便首先补偿集成电路（IC）“从”）接合器中的变量，并且其次是位于从属接合器上的“从”电路中的任何不规则性，用于将连接键附接到 IC焊盘。 根据本发明，“主”分隔器将主接头上的“主”电路的接合焊盘分组成段，并将与这些段相关的参考数据存储在主文件中。 接下来，耦合到主文件的从再生器重新生成主参考数据，从而定义从属接合器的可变特性并进行自适应补偿。 最后，耦合到硬盘再生器的从属校正器在自适应补偿的从属接合器上校正从电路的接合程序。 奴隶连接器根据计算的正确的债券位置附加连接债券。

公开(公告)号：US20060049492A1

公开(公告)日：2006-03-09

申请号：US11114565

申请日：2005-04-25

申请人： Jeffrey Holloway ,  Sreenivasan Koduri

发明人： Jeffrey Holloway ,  Sreenivasan Koduri

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L23/49805 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for a reduced foot print package with tolerance for thermal and mechanical stresses for integrated circuits. A preferred embodiment comprises a package for an integrated circuit die comprising a plurality of input/output contacts and a die support to hold the integrated circuit die. The die support comprises a plurality of support arms, wherein each support arm is electrically disjoint and having an end with an exposed fuse lead that will be external of the packaged integrated circuit die. The exposed fuse leads can be used to fix the packaged integrated circuit die to a substrate and provide additional bonding strength to increase tolerance to thermal and mechanical stresses.

摘要翻译： 用于集成电路的用于热和机械应力公差的减少的脚印封装的系统和方法。 优选实施例包括用于集成电路管芯的封装，其包括多个输入/输出触点和用于保持集成电路管芯的管芯支撑件。 模具支撑件包括多个支撑臂，其中每个支撑臂是电不相交的，并且其端部具有将被封装的集成电路管芯外部的暴露的熔丝引线。 暴露的保险丝引线可用于将封装的集成电路管芯固定到基板上，并提供额外的接合强度，以增加对热和机械应力的耐受性。

公开(公告)号：US20060006510A1

公开(公告)日：2006-01-12

申请号：US10886352

申请日：2004-07-06

申请人： Sreenivasan Koduri

发明人： Sreenivasan Koduri

IPC分类号： H01L23/02

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/48664 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85464 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Plastic encapsulated semiconductor devices having elevated topographical features on the chip mount pad to control the extent of delamination at the plastic to substrate interface, thereby allowing reliable down bond sites to be formed on the top surface of the chip mount pad which may serve as a ground plane. The cost effective invention is applicable to a variety of semiconductor packages, including both leaded and non-leaded types for high frequency circuits.

摘要翻译： 塑料封装的半导体器件在芯片安装焊盘上具有升高的形貌特征，以控制在塑料与衬底界面之间的分层程度，从而允许在可用作接地的芯片安装焊盘的顶部表面上形成可靠的下降键合位置 飞机 成本有效的发明适用于各种半导体封装，包括用于高频电路的引线型和非引线型。

公开(公告)号：US20050121372A1

公开(公告)日：2005-06-09

申请号：US11036714

申请日：2005-01-14

申请人： Sreenivasan Koduri ,  Matthew Stovall

发明人： Sreenivasan Koduri ,  Matthew Stovall

IPC分类号： H01L21/00 ,  B07C5/344 ,  G01R31/02

CPC分类号： H01L21/67271 ,  H01L21/67132 ,  H01L21/67144

摘要： Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include picking and removing all of the bad parts from a wafer before picking the good parts and picking all of the good parts first without picking any part necessary to align the wafer. The equipment includes several embodiments of a transfer machine that accommodates the efficient transfer of semiconductor parts between tacky film, waffle packs and tape and reel containment systems. Residual good parts are stored in waffle packs and can be subsequently reused in the packaging process.