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11.发明授权High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer 有权高K金属栅极电极结构通过盖层去除形成而不需要牺牲间隔物公开(公告)号：US08987144B2
公开(公告)日：2015-03-24
申请号：US13198107
申请日：2011-08-04
IPC分类号： H01L21/302 , H01L21/8238 , H01L21/311 , H01L29/165 , H01L29/66 , H01L29/78 , H01L21/3115
CPC分类号： H01L21/823864 , H01L21/31116 , H01L21/31155 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
摘要翻译： 在复杂的半导体器件中，高k金属栅极电极结构可以在早期制造阶段形成，其中敏感栅极材料的完整性通过在选定的活性区域中选择性沉积应变诱导半导体材料之后提供附加的衬垫材料。 此外，可以基于通过避免图案化和去除任何牺牲氧化物间隔物而显着降低隔离区域和有源区域中的材料侵蚀程度的工艺流程来去除栅电极结构的电介质盖材料。
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12.发明授权Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography 有权半导体器件包括形成有减少的STI形貌的沟道半导体合金公开(公告)号：US08748275B2
公开(公告)日：2014-06-10
申请号：US13191993
申请日：2011-07-27
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/76232 , H01L21/823878
摘要： In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.
摘要翻译： 在复杂的半导体器件中，半导体合金，例如硅/锗形式的阈值调节半导体材料，可以在早期制造阶段中选择性地在某些活性区域中提供，其中明显的凹陷程度和材料损失 在隔离区域中，可以通过在隔离区域上选择性地提供保护材料层来避免。 例如，在一些说明性实施例中，硅材料可以选择性地沉积在隔离区域上。
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13.发明授权公开(公告)号：US08722479B2
公开(公告)日：2014-05-13
申请号：US13115270
申请日：2011-05-25
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L21/823842 , H01L21/84 , H01L27/10894 , H01L27/1203
摘要： Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.
摘要翻译： 通常，本公开涉及一种在制造期间至少减少半导体器件的隔离结构的不希望的侵蚀的方法。 所公开的一种说明性方法包括在半导体衬底中形成隔离结构，并在多个隔离结构之上形成导电保护环。
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14.发明申请Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography 有权包含形成减少STI地形的通道半导体合金的半导体器件公开(公告)号：US20120156846A1
公开(公告)日：2012-06-21
申请号：US13191993
申请日：2011-07-27
IPC分类号： H01L21/8234 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/76232 , H01L21/823878
摘要： In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.
摘要翻译： 在复杂的半导体器件中，半导体合金，例如硅/锗形式的阈值调节半导体材料，可以在早期制造阶段中选择性地在某些活性区域中提供，其中明显的凹陷程度和材料损失 在隔离区域中，可以通过在隔离区域上选择性地提供保护材料层来避免。 例如，在一些说明性实施例中，硅材料可以选择性地沉积在隔离区域上。
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15.发明授权Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping 有权通过后期栅极掺杂增强半导体器件的栅电极的图案均匀性公开(公告)号：US09281200B2
公开(公告)日：2016-03-08
申请号：US13189997
申请日：2011-07-25
申请人： Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
发明人： Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/265 , H01L21/8234 , H01L29/49
CPC分类号： H01L21/28123 , H01L21/265 , H01L21/28035 , H01L21/82345 , H01L21/823842 , H01L29/4916
摘要： When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.
摘要翻译： 当形成晶体管的复杂的基于半导体的栅极电极结构时，一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式，在选择适当的图案化状态方面提供了高度的柔性，同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。
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16.发明授权Reticles for use in forming implant masking layers and methods of forming implant masking layers 有权用于形成植入物掩模层的网状物和形成植入物掩蔽层的方法公开(公告)号：US08802360B2
公开(公告)日：2014-08-12
申请号：US13560012
申请日：2012-07-27
申请人： Martin Mazur , Henke Dietmar , Hans-Juergen Thees
发明人： Martin Mazur , Henke Dietmar , Hans-Juergen Thees
IPC分类号： G03F7/20
CPC分类号： G03F1/24 , G03F1/22 , G03F1/50 , G03F7/2026 , G03F7/2045
摘要： In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.
摘要翻译： 在一个示例中，本文公开的掩模版包括具有中心的主体，多个曝光图案的布置，其中该布置的中心偏离主体的中心，以及限定在该主体上或之上的至少一个开放特征 标线的主体。 在另一个实例中，公开了一种方法，其包括在多个功能模具上形成光致抗蚀剂层和多个不完全模具，使位于功能模具中的至少一个上的光致抗蚀剂材料和/或至少一个不完全模具 通过掩模版的开放特征执行不完全的裸片曝光处理，以露出位于多个不完全裸片上方的基本上所有的光致抗蚀剂材料，并且显影光致抗蚀剂以去除位于不完全裸片上方的光刻胶材料的部分。
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公开(公告)号：US20130015527A1
公开(公告)日：2013-01-17
申请号：US13180655
申请日：2011-07-12
申请人： Hans-Juergen Thees , Peter Baars
发明人： Hans-Juergen Thees , Peter Baars
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/76889 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/4232 , H01L29/4975 , H01L29/78
摘要： The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer. The method further includes forming a layer of material above and between the gate electrodes, wherein the layer of material has an upper surface that is positioned higher than an upper surface of each of the gate electrodes, performing a first etching process on the layer of material to reduce a thickness thereof such that the upper surface of the layer of material is positioned at a desired level that is at least below the upper surface of each of the gate electrodes, and after performing the first etching process, performing a second etching process to insure that a desired amount of the gate electrodes for the PMOS transistor and the NMOS transistor are exposed for a subsequent metal silicide formation process. The method concludes with the step of forming metal silicide regions on the gate electrode structures and on the source/drain regions.
摘要翻译： 本公开涉及在集成电路器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括形成PMOS晶体管和NMOS晶体管，每个晶体管具有栅极电极和形成在半导体衬底中的至少一个源极/漏极区域，形成邻近栅电极的第一侧壁间隔物并形成 邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括在栅电极之上和之间形成一层材料，其中该材料层具有位于每个栅电极的上表面的上表面，对该材料层进行第一蚀刻工艺 为了减小其厚度，使得材料层的上表面位于至少低于每个栅电极的上表面的期望水平，并且在执行第一蚀刻工艺之后，执行第二蚀刻工艺 确保用于PMOS晶体管和NMOS晶体管的期望量的栅电极暴露于随后的金属硅化物形成工艺。 该方法的结论是在栅极电极结构和源极/漏极区域上形成金属硅化物区域的步骤。
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公开(公告)号：US08859356B2
公开(公告)日：2014-10-14
申请号：US13180655
申请日：2011-07-12
申请人： Hans-Juergen Thees , Peter Baars
发明人： Hans-Juergen Thees , Peter Baars
IPC分类号： H01L21/8238 , H01L29/78 , H01L21/768
CPC分类号： H01L27/092 , H01L21/76889 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/4232 , H01L29/4975 , H01L29/78
摘要： The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer. The method further includes forming a layer of material above and between the gate electrodes, wherein the layer of material has an upper surface that is positioned higher than an upper surface of each of the gate electrodes, performing a first etching process on the layer of material to reduce a thickness thereof such that the upper surface of the layer of material is positioned at a desired level that is at least below the upper surface of each of the gate electrodes, and after performing the first etching process, performing a second etching process to insure that a desired amount of the gate electrodes for the PMOS transistor and the NMOS transistor are exposed for a subsequent metal silicide formation process. The method concludes with the step of forming metal silicide regions on the gate electrode structures and on the source/drain regions.
摘要翻译： 本公开涉及在集成电路器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括形成PMOS晶体管和NMOS晶体管，每个晶体管具有栅极电极和形成在半导体衬底中的至少一个源极/漏极区域，形成邻近栅电极的第一侧壁间隔物并形成 邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括在栅电极之上和之间形成一层材料，其中该材料层具有位于每个栅电极的上表面的上表面，对该材料层进行第一蚀刻工艺 以减小其厚度，使得材料层的上表面位于至少在每个栅电极的上表面下方的期望水平，并且在执行第一蚀刻工艺之后，执行第二蚀刻工艺 确保用于PMOS晶体管和NMOS晶体管的期望量的栅电极暴露于随后的金属硅化物形成工艺。 该方法的结论是在栅极电极结构和源极/漏极区域上形成金属硅化物区域的步骤。
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19.发明申请RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF FORMING IMPLANT MASKING LAYERS 有权用于形成植入掩膜层的形态和形成植入物掩膜层的方法公开(公告)号：US20140030637A1
公开(公告)日：2014-01-30
申请号：US13560012
申请日：2012-07-27
申请人： Martin Mazur , Henke Dietmar , Hans-Juergen Thees
发明人： Martin Mazur , Henke Dietmar , Hans-Juergen Thees
CPC分类号： G03F1/24 , G03F1/22 , G03F1/50 , G03F7/2026 , G03F7/2045
摘要： In one example, a reticle disclosed herein includes a body having a center, an arrangement of a plurality of exposure patterns, wherein a center of the arrangement is offset from the center of the body, and at least one open feature defined on or through the body of the reticle. In another example, a method is disclosed that includes forming a layer of photoresist above a plurality of functional die and a plurality of incomplete die, exposing the photoresist material positioned above at least one of the functional die and/or at least one of the incomplete die, performing an incomplete die exposure processes via an open feature of the reticle to expose substantially all of the photoresist material positioned above the plurality of incomplete die, and developing the photoresist to remove the portions of the photoresist material positioned above the incomplete die.
摘要翻译： 在一个示例中，本文公开的掩模版包括具有中心的主体，多个曝光图案的布置，其中该布置的中心偏离主体的中心，以及限定在该主体上或之上的至少一个开放特征 标线的主体。 在另一个实例中，公开了一种方法，其包括在多个功能模具上形成光致抗蚀剂层和多个不完全模具，使位于功能模具中的至少一个上的光致抗蚀剂材料和/或至少一个不完全模具 通过掩模版的开放特征执行不完全的裸片曝光处理，以露出位于多个不完全裸片上方的基本上所有的光致抗蚀剂材料，并且显影光致抗蚀剂以去除位于不完全裸片上方的光刻胶材料的部分。
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20.发明申请Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping 有权通过晚期栅极掺杂增强半导体器件的栅极电极的图案化均匀性公开(公告)号：US20120156865A1
公开(公告)日：2012-06-21
申请号：US13189997
申请日：2011-07-25
申请人： Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
发明人： Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
IPC分类号： H01L21/28
CPC分类号： H01L21/28123 , H01L21/265 , H01L21/28035 , H01L21/82345 , H01L21/823842 , H01L29/4916
摘要： When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.
摘要翻译： 当形成晶体管的复杂的基于半导体的栅极电极结构时，一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式，在选择适当的图案化状态方面提供了高度的柔性，同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。
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