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93 条记录 (耗时 0.026 秒)

    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas
    11.
    发明申请
    Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas 有权
    包括高K金属栅电极结构的互补晶体管和排水和源区域中的外延形成的半导体材料

    公开(公告)号：US20120211838A1

    公开(公告)日：2012-08-23

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy forN-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。

    Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material
    12.
    发明申请
    Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material 有权
    通过盖层去除形成的复杂的门极电极结构，减少嵌入式应变诱导半导体材料的损耗

    公开(公告)号：US20120196417A1

    公开(公告)日：2012-08-02

    申请号：US13358101

    申请日：2012-01-25

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski ,  Frank Seliger ,  Frank Richter

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

    摘要翻译： 当形成诸如高k金属栅电极结构的复杂的栅电极结构时，可以实现适当的封装，同时也可以避免在一种晶体管中提供的应变诱导半导体材料的不适当的材料损耗。 为此，可以在沉积应变诱导半导体材料之前对保护间隔物结构进行图案化，其基于相同的工艺流程，对于每种类型的晶体管，在应变诱导半导体材料沉积之后， 可以提供蚀刻停止层，以便保持活性区域的完整性。

    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION
    15.
    发明申请
    TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION 有权
    具有嵌入式SI / GE材料的晶体管具有减少偏移到通道区域

    公开(公告)号：US20100078689A1

    公开(公告)日：2010-04-01

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas
    16.
    发明授权
    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas 有权
    在漏极和源极区域中包括高k金属栅电极结构和外延形成的半导体材料的互补晶体管

    公开(公告)号：US08835209B2

    公开(公告)日：2014-09-16

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L21/00 ,  H01L21/70 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。

    Superior stability of characteristics of transistors having an early formed high-K metal gate
    17.
    发明授权
    Superior stability of characteristics of transistors having an early formed high-K metal gate 有权
    具有早期形成的高K金属栅极的晶体管的特性的优异的稳定性

    公开(公告)号：US08652917B2

    公开(公告)日：2014-02-18

    申请号：US13478519

    申请日：2012-05-23

    申请人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    发明人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02057 ,  H01L21/0209 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/7848

    摘要： When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.

    摘要翻译： 当在高k金属栅电极结构和应变诱导半导体合金的基础上形成复杂的晶体管时，在形成空腔之后应用优良的湿式清洗工艺策略，以减少敏感栅极材料的过度修改， k电介质材料，含金属的电极材料等，以及阈值电压调整用半导体合金的变形例。 因此，与常规策略相比，不同宽度的晶体管的阈值电压的显着依赖性可以显着降低。

    Transistor with embedded Si/Ge material having reduced offset to the channel region
    18.
    发明授权
    Transistor with embedded Si/Ge material having reduced offset to the channel region 有权
    具有嵌入的Si / Ge材料的晶体管具有减小到沟道区的偏移

    公开(公告)号：US08071442B2

    公开(公告)日：2011-12-06

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。