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    Superior stability of characteristics of transistors having an early formed high-K metal gate
    1.
    发明授权
    Superior stability of characteristics of transistors having an early formed high-K metal gate 有权
    具有早期形成的高K金属栅极的晶体管的特性的优异的稳定性

    公开(公告)号：US08652917B2

    公开(公告)日：2014-02-18

    申请号：US13478519

    申请日：2012-05-23

    申请人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    发明人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02057 ,  H01L21/0209 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/7848

    摘要： When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.

    摘要翻译： 当在高k金属栅电极结构和应变诱导半导体合金的基础上形成复杂的晶体管时，在形成空腔之后应用优良的湿式清洗工艺策略，以减少敏感栅极材料的过度修改， k电介质材料，含金属的电极材料等，以及阈值电压调整用半导体合金的变形例。 因此，与常规策略相比，不同宽度的晶体管的阈值电压的显着依赖性可以显着降低。

    SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE
    2.
    发明申请
    SUPERIOR STABILITY OF CHARACTERISTICS OF TRANSISTORS HAVING AN EARLY FORMED HIGH-K METAL GATE 有权
    具有早期形成的高K金属栅的晶体管特性的超稳定性

    公开(公告)号：US20130316511A1

    公开(公告)日：2013-11-28

    申请号：US13478519

    申请日：2012-05-23

    申请人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    发明人： Markus Lenski ,  Stephan Kronholz ,  Nadja Zakowsky

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02057 ,  H01L21/0209 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/7848

    摘要： When forming sophisticated transistors on the basis of a high-k metal gate electrode structure and a strain-inducing semiconductor alloy, a superior wet cleaning process strategy is applied after forming cavities in order to reduce undue modification of sensitive gate materials, such as high-k dielectric materials, metal-containing electrode materials and the like, and modification of a threshold voltage adjusting semiconductor alloy. Thus, the pronounced dependence of the threshold voltage of transistors of different width may be significantly reduced compared to conventional strategies.

    摘要翻译： 当在高k金属栅电极结构和应变诱导半导体合金的基础上形成复杂的晶体管时，在形成空腔之后应用优良的湿式清洗工艺策略，以减少敏感栅极材料的过度修改， k电介质材料，含金属的电极材料等，以及阈值电压调整用半导体合金的变形例。 因此，与常规策略相比，不同宽度的晶体管的阈值电压的显着依赖性可以显着降低。

    EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES
    3.
    发明申请
    EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES 有权
    外来通道形成方法和结构

    公开(公告)号：US20130210216A1

    公开(公告)日：2013-08-15

    申请号：US13369856

    申请日：2012-02-09

    申请人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    发明人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66651 ,  H01L21/02035 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7833

    摘要： A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

    摘要翻译： 在每个批处理反应器的多个晶片中形成场效应晶体管（FET）的方法包括：在其中提供具有至少一个具有基本上平坦的外表面的至少一个半导体（SC）区域的衬底，修改该基本平坦的外表面以形成凸 在曲面上形成外延半导体层，并且在形成在基板上的场效应晶体管中并入外延层。 当SC区域是硅时，外延层可以包括硅 - 锗。 在优选实施例中，外延层形成FET通道的一部分。 由于凸向外弯曲的表面，即使在每批容纳多达100个或更多个基底的高体积反应器中形成时，其上生长的外延层也具有更均匀的厚度。 获得具有更均匀性能的FET，从而大大提高制造成品率并降低成本。

    Epitaxial channel formation methods and structures
    4.
    发明授权
    Epitaxial channel formation methods and structures 有权
    外延通道形成方法和结构

    公开(公告)号：US09548378B2

    公开(公告)日：2017-01-17

    申请号：US13369856

    申请日：2012-02-09

    申请人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    发明人： Stephan Kronholz ,  Nadja Zakowsky ,  Yew Tuck Chow

    IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

    CPC分类号： H01L29/66651 ,  H01L21/02035 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7833

    摘要： A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

    摘要翻译： 在每个批处理反应器的多个晶片中形成场效应晶体管（FET）的方法包括：在其中提供具有至少一个具有基本上平坦的外表面的至少一个半导体（SC）区域的衬底，修改该基本平坦的外表面以形成凸 在曲面上形成外延半导体层，并且在形成在基板上的场效应晶体管中并入外延层。 当SC区域是硅时，外延层可以包括硅 - 锗。 在优选实施例中，外延层形成FET通道的一部分。 由于凸向外弯曲的表面，即使在每批容纳多达100个或更多个基底的高体积反应器中形成时，其上生长的外延层也具有更均匀的厚度。 获得具有更均匀性能的FET，从而大大提高制造成品率并降低成本。

    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas
    5.
    发明授权
    Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas 有权
    在漏极和源极区域中包括高k金属栅电极结构和外延形成的半导体材料的互补晶体管

    公开(公告)号：US08835209B2

    公开(公告)日：2014-09-16

    申请号：US13370944

    申请日：2012-02-10

    申请人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    发明人： Stephan Kronholz ,  Gunda Beernink ,  Markus Lenski

    IPC分类号： H01L21/00 ,  H01L21/70 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

    摘要翻译： 当形成包括具有减小的栅极长度的互补晶体管的复杂半导体器件时，可以基于单独提供的半导体合金（例如用于P沟道晶体管的硅/锗合金）和用于磷/磷半导体合金的硅/磷半导体合金 N沟道晶体管。 为此，可以应用优异的硬掩模图案化方案，以提供与复杂的替代栅极方法的兼容性，同时避免不适当的工艺不均匀性，特别是关于去除电介质盖层。

    Transistor with embedded Si/Ge material having reduced offset to the channel region
    6.
    发明授权
    Transistor with embedded Si/Ge material having reduced offset to the channel region 有权
    具有嵌入的Si / Ge材料的晶体管具有减小到沟道区的偏移

    公开(公告)号：US08071442B2

    公开(公告)日：2011-12-06

    申请号：US12552642

    申请日：2009-09-02

    申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

    摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

    摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。