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    FRET-LABELED COMPOUNDS AND USES THEREFOR
    11.
    发明申请
    FRET-LABELED COMPOUNDS AND USES THEREFOR 审中-公开
    FRET-LABELED化合物及其用途

    公开(公告)号：US20130071849A1

    公开(公告)日：2013-03-21

    申请号：US13427611

    申请日：2012-03-22

    申请人： Xiangxu Kong ,  Gene Shen

    发明人： Xiangxu Kong ,  Gene Shen

    IPC分类号： G01N21/64

    CPC分类号： C12Q1/6818 ,  C07H19/207 ,  C12Q1/6869 ,  G01N21/6428 ,  G01N33/542 ,  G01N33/582 ,  G01N2021/6441 ,  Y10T436/143333

    摘要： FRET-labeled compounds are provided for use in analytical reactions. In certain embodiments, FRET-labeled nucleotide analogs are used in place of naturally occurring nucleoside triphosphates or other analogs in analytical reactions comprising nucleic acids, for example, template-directed nucleic acid synthesis, DNA sequencing, RNA sequencing, single-base identification, hybridization, binding assays, and other analytical reactions.

    摘要翻译： 提供FRET标记的化合物用于分析反应。 在某些实施方案中，FRET标记的核苷酸类似物用于代替包含核酸的分析反应中天然存在的核苷三磷酸或其它类似物，例如模板指导的核酸合成，DNA测序，RNA测序，单碱基鉴定，杂交 ，结合测定和其他分析反应。

    ENGINEERED FLUORESCENT DYE LABELED NUCLEOTIDE ANALOGS FOR DNA SEQUENCING
    13.
    发明申请
    ENGINEERED FLUORESCENT DYE LABELED NUCLEOTIDE ANALOGS FOR DNA SEQUENCING 有权
    用于DNA测序的工程化荧光染料标记核苷类似物

    公开(公告)号：US20120028248A1

    公开(公告)日：2012-02-02

    申请号：US13115284

    申请日：2011-05-25

    申请人： Gene Shen ,  Paul Peluso ,  Arkadusz Bibillo

    发明人： Gene Shen ,  Paul Peluso ,  Arkadusz Bibillo

    IPC分类号： C12Q1/68 ,  C07H19/207 ,  C07H19/10

    CPC分类号： C07H19/04

    摘要： Engineered nucleotide compositions, having polymerase interacting components that improve the interactivity of the polymerase and the nucleotide, particularly for nucleic acid sequencing applications. Compositions include the interactive polymerases along with the nucleotide analogs. Kits, methods and systems are provided for analysis of nucleoc acid synthesis reactions.

    摘要翻译： 具有改进聚合酶和核苷酸的相互作用的聚合酶相互作用组分的工程化核苷酸组合物，特别是用于核酸测序应用。 组合物包括与核苷酸类似物一起的交互聚合酶。 提供试剂盒，方法和系统用于分析核酸合成反应。

    Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes
    15.
    发明授权
    Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes 失效
    在具有部分寄存器写入的超标量处理器中减少了配对指令调度的寄存器依赖性检查

    公开(公告)号：US5790826A

    公开(公告)日：1998-08-04

    申请号：US618636

    申请日：1996-03-19

    申请人： Shalesh Thusoo ,  Gene Shen ,  James S. Blomgren

    发明人： Shalesh Thusoo ,  Gene Shen ,  James S. Blomgren

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/28

    CPC分类号： G06F9/30043 ,  G06F9/30112 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857

    摘要： The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the following instructions' sources, but the destinations of following instructions are not checked with the first instruction's destination. Instead, instructions with destination-destination dependencies are dispatched together as a group. These instructions flow down the pipelines. At the end of the pipelines the destinations are compared. If the destinations match then the results are merged together and written to the register. When instructions write to only a portion of the register, merging ensures that the correct portions of the register are written by the appropriate instructions in the group. Thus older code which performs partial-register writes can benefit from superscalar processing by dispatching the instructions together as a group and then merging the writes together at the end of the pipelines. The dispatch and decode stage, which is often a critical path on the processor, is reduced in complexity by not checking for destination-register dependencies. Performance increases because more kinds of instructions can be dispatched together in a group, increasing the use of the superscalar features.

    摘要翻译： 超标量处理器的调度单元检查要作为一组发放在一起的指令之间的寄存器依赖性。 第一个指令的目的地寄存器与以下指令的源进行比较，但是第一个指令的目的地不检查以下指令的目的地。 相反，具有目的地 - 目的地依赖关系的指令一起作为一组分派。 这些指令沿着管道流下。 在管道末端比较目的地。 如果目的地匹配，则结果合并在一起并写入寄存器。 当指令仅写入寄存器的一部分时，合并确保寄存器的正确部分由组中的相应指令写入。 因此，执行部分寄存器写入的较旧的代码可以通过将指令一起发送为一组然后在管道末端合并在一起的超标量处理而受益。 调度和解码阶段（通常是处理器上的关键路径）通过不检查目标寄存器依赖关系来降低复杂度。 性能提高，因为可以在一组中一起调度更多种类的指令，从而增加超标量特征的使用。

    Mixed-modulo address generation using shadow segment registers
    16.
    发明授权
    Mixed-modulo address generation using shadow segment registers 失效
    使用影子段寄存器的混合模地址生成

    公开(公告)号：US5790443A

    公开(公告)日：1998-08-04

    申请号：US618632

    申请日：1996-03-19

    申请人： Gene Shen ,  Shalesh Thusoo ,  James S. Blomgren ,  Betty Kikuta

    发明人： Gene Shen ,  Shalesh Thusoo ,  James S. Blomgren ,  Betty Kikuta

    IPC分类号： G06F7/50 ,  G06F7/509 ,  G06F9/30 ,  G06F9/355 ,  G06F12/02 ,  G06F7/38 ,  G06F9/26

    CPC分类号： G06F9/30116 ,  G06F12/0292 ,  G06F7/509 ,  G06F9/3013 ,  G06F9/355 ,  G06F9/3552 ,  G06F7/49931 ,  G06F7/49994

    摘要： A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width address components such as 16-bit address components which are effectively added together in modulo 64K. The other inputs receive full-width address components such as 32-bit components which are added in the full modulus, 4G. Reduced-width components are zero-extended to 32 bits before input to a standard 32-bit adder. A 16-bit carry generator also receives the reduced-width components and generates the carries out of the 16th bit position. When one or more carries is detected, a correction term is subtracted from the initial sum which is recirculated to the adder's input in a subsequent step. The correction term is the number of carries out of the 16th bit position multiplied by 64K. The full-width segment bases for all active segments are stored in the register file, but the most commonly accessed segments, the data and stack segments, have a copy of their segment bases also stored in a shadow register for input to the adder. Thus the number of read ports to the register file is reduced by the shadow segment register. Less-frequently-used segments require an additional step through the adder to generate the address, but addresses in the data and stack segments are generated in a single cycle.

    摘要翻译： 混合模地址生成单元具有多个输入。 该单元有效地将减少的模数中的这些输入的子集合在一起，同时将全模数的其他输入添加到减模量输入的部分和。 输入子集接收减少宽度的地址组件，例如16位地址组件，这些组件以64K模式实际加在一起。 其他输入接收全宽地址组件，例如以完全模数4G格式添加的32位组件。 在输入到标准32位加法器之前，缩减宽度分量将零扩展到32位。 16位进位发生器还接收减小宽度分量并产生第16位位置的执行。 当检测到一个或多个载波时，在随后的步骤中从初始和减去校正项，该初始和再循环到加法器的输入。 校正项是执行第16位位乘以64K的次数。 所有活动段的全宽段基准存储在寄存器文件中，但是最常访问的段，数据和堆栈段都具有其段基准的副本，也存储在阴影寄存器中，以输入加法器。 因此，通过影子段寄存器减少寄存器文件的读端口数。 较不频繁使用的分段需要通过加法器的附加步骤来生成地址，但是在单个周期中生成数据和堆栈段中的地址。

    Engineered fluorescent dye labeled nucleotide analogs for DNA sequencing
    18.
    发明授权
    Engineered fluorescent dye labeled nucleotide analogs for DNA sequencing 有权
    用于DNA测序的工程荧光染料标记的核苷酸类似物

    公开(公告)号：US08133702B2

    公开(公告)日：2012-03-13

    申请号：US13115284

    申请日：2011-05-25

    申请人： Gene Shen ,  Paul Peluso ,  Arkadusz Bibillo

    发明人： Gene Shen ,  Paul Peluso ,  Arkadusz Bibillo

    IPC分类号： C12P19/34 ,  C12Q1/68 ,  C07H21/00

    CPC分类号： C07H19/04

    摘要： Engineered nucleotide compositions, having polymerase interacting components that improve the interactivity of the polymerase and the nucleotide, particularly for nucleic acid sequencing applications. Compositions include the interactive polymerases along with the nucleotide analogs. Kits, methods and systems are provided for analysis of nucleic acid synthesis reactions.

    摘要翻译： 具有改进聚合酶和核苷酸的相互作用的聚合酶相互作用组分的工程化核苷酸组合物，特别是用于核酸测序应用。 组合物包括与核苷酸类似物一起的交互聚合酶。 提供了用于分析核酸合成反应的试剂盒，方法和系统。

    Processing pipeline having stage-specific thread selection and method thereof
    19.
    发明授权
    Processing pipeline having stage-specific thread selection and method thereof 有权
    具有阶段特定线程选择的处理管线及其方法

    公开(公告)号：US08086825B2

    公开(公告)日：2011-12-27

    申请号：US11967923

    申请日：2007-12-31

    申请人： Gene Shen ,  Sean Lie ,  Marius Evers

    发明人： Gene Shen ,  Sean Lie ,  Marius Evers

    IPC分类号： G06F9/38 ,  G06F9/48

    CPC分类号： G06F9/3867 ,  G06F9/3851 ,  G06F9/3891

    摘要： One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.

    摘要翻译： 多核处理设备的一个或多个处理器核心可以利用具有多个执行单元（例如，整数执行单元或浮点单元）的处理流水线，这些执行单元共同共享具有指令获取的前执行前端，解码 并派遣资源。 此外，一个或多个处理器核心可以实现调度资源，配置为通过分开的调度总线并行分配多个相应执行单元的多个指令。 调度资源还可以并行地从多个线程机会地解码和分派指令操作，以增加调度带宽。 此外，一个或多个处理器核心的处理流水线的一些或所有阶段可被配置为实现相应阶段的独立线程选择。

    Processing pipeline having parallel dispatch and method thereof
    20.
    发明授权
    Processing pipeline having parallel dispatch and method thereof 有权
    具有并行调度的处理流水线及其方法

    公开(公告)号：US07793080B2

    公开(公告)日：2010-09-07

    申请号：US11967924

    申请日：2007-12-31

    申请人： Gene Shen ,  Sean Lie

    发明人： Gene Shen ,  Sean Lie

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3885 ,  G06F9/3822 ,  G06F9/3842 ,  G06F9/3851

    摘要： One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages of the processing pipelines of one or more of the processor cores can be configured to implement independent thread selection for the corresponding stage.

    摘要翻译： 多核处理设备的一个或多个处理器核心可以利用具有多个执行单元（例如，整数执行单元或浮点单元）的处理流水线，这些执行单元共同共享具有指令获取的解码器的前执行前端 并派遣资源。 此外，一个或多个处理器核心可以实现调度资源，配置为通过分开的调度总线并行分配多个相应执行单元的多个指令。 调度资源还可以并行地从多个线程机会地解码和分派指令操作，以增加调度带宽。 此外，一个或多个处理器核心的处理流水线的一些或所有阶段可被配置为实现相应阶段的独立线程选择。