公开(公告)号：US09728598B2

公开(公告)日：2017-08-08

申请号：US14681045

申请日：2015-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： I-Chih Chen ,  Chih-Mu Huang ,  Fu-Tsun Tsai ,  Meng-Yi Wu ,  Yung-Fa Lee ,  Ying-Lang Wang

IPC: H01L21/425 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/0638 ,  H01L21/26506 ,  H01L29/0603 ,  H01L29/0847 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

公开(公告)号：US09591242B2

公开(公告)日：2017-03-07

申请号：US13944629

申请日：2013-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Volume Chien ,  Yun-Wei Cheng ,  Che-Min Lin ,  Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC: H04N5/361 ,  H01L27/146

CPC classification number: H04N5/361 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/1464

Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.

Abstract translation: 实施例图像传感器包括通过缓冲区域与黑电平控制（BLC）区域间隔开的像素区域。 在一个实施例中，遮光罩设置在BLC区域上并延伸到缓冲区域中。 在一个实施例中，缓冲区包括虚拟像素阵列。 这样的实施例有效地减少了在BLC区域的边缘处的光串扰，这允许更准确的黑电平校准。 因此，图像传感器能够产生更高质量的图像。

公开(公告)号：US09543399B2

公开(公告)日：2017-01-10

申请号：US14245795

申请日：2014-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Yao-Tsung Chen ,  Ming-Tsang Tsai ,  Kuan-Yu Chen

IPC: H01L21/4763 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833

Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.

Abstract translation: 提供具有开放型型栅电极的半导体器件及其制造方法。 漏斗形的开口形成在电介质层中，并且在漏斗形开口中形成栅电极，从而提供具有开口形状的栅电极。 在一些实施例中，第一和第二栅极间隔物与虚拟栅电极一起形成。 去除虚拟栅电极，去除第一和第二栅极间隔物的上部。 第一和第二栅极间隔物可以由具有不同蚀刻速率的不同材料形成。

公开(公告)号：US09450014B2

公开(公告)日：2016-09-20

申请号：US14840143

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-I Cheng ,  Chih-Mu Huang ,  Pin Chia Su ,  Chi-Cherng Jeng ,  Volume Chien ,  Chih-Kang Chao

IPC: H01L27/02 ,  H01L27/146 ,  H01L27/14 ,  H01L21/82 ,  H01L23/58

CPC classification number: H01L27/14645 ,  H01L21/82 ,  H01L23/585 ,  H01L27/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

公开(公告)号：US09246002B2

公开(公告)日：2016-01-26

申请号：US14208294

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Kang Chao ,  Chen-Chieh Chiang

IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer.

Abstract translation: 公开了半导体器件及其形成方法。 半导体器件包括衬底，以及形成在衬底中的源区和漏区。 半导体器件还包括形成在源极区域和漏极区域之间的衬底的凹部中的杂质扩散停止层，其中杂质扩散停止层覆盖凹部的底部和侧壁。 半导体器件还包括形成在杂质扩散停止层上和凹槽中的沟道层，以及形成在沟道层上的栅叠层。 杂质扩散阻挡层基本上防止了衬底和源区和漏区的杂质扩散到沟道层。

公开(公告)号：US20150287798A1

公开(公告)日：2015-10-08

申请号：US14245795

申请日：2014-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Yao-Tsung Chen ,  Ming-Tsang Tsai ,  Kuan-Yu Chen

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833

Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.

Abstract translation: 提供具有开放型型栅电极的半导体器件及其制造方法。 漏斗形的开口形成在电介质层中，并且在漏斗形开口中形成栅电极，从而提供具有开口形状的栅电极。 在一些实施例中，第一和第二栅极间隔物与虚拟栅电极一起形成。 去除虚拟栅电极，去除第一和第二栅极间隔物的上部。 第一和第二栅极间隔物可以由具有不同蚀刻速率的不同材料形成。

公开(公告)号：US20150263168A1

公开(公告)日：2015-09-17

申请号：US14208294

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Chih-Kang Chao ,  Chen-Chieh Chiang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer. The impurity diffusion stop layer substantially prevents impurities of the substrate and the source and drain regions from diffusing into the channel layer.

Abstract translation: 公开了半导体器件及其形成方法。 半导体器件包括衬底，以及形成在衬底中的源区和漏区。 半导体器件还包括形成在源极区域和漏极区域之间的衬底的凹部中的杂质扩散停止层，其中杂质扩散停止层覆盖凹部的底部和侧壁。 半导体器件还包括形成在杂质扩散停止层上和凹槽中的沟道层，以及形成在沟道层上的栅叠层。 杂质扩散阻挡层基本上防止了衬底和源区和漏区的杂质扩散到沟道层。

公开(公告)号：US20150241768A1

公开(公告)日：2015-08-27

申请号：US14192225

申请日：2014-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Shang Hsiao ,  I-I Cheng ,  Jia-Ming Huang ,  Jen-Pan Wang ,  Ling-Sung Wang ,  Chih-Mu Huang

IPC: G03F1/42 ,  H01L21/027 ,  G06T7/00 ,  H01L23/544

CPC classification number: G03F1/42 ,  G06T7/001 ,  G06T2207/30148 ,  G06T2207/30204 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first material formed on a substrate. The first material includes a first alignment mark. The first alignment mark includes alignment lines in at least three directions. The semiconductor device further includes a second material comprising a second alignment mark. The second alignment mark corresponds to the first alignment mark such that when the second alignment mark is aligned with the first alignment mark, the second material is aligned with the first material.

Abstract translation: 半导体器件包括形成在衬底上的第一材料。 第一材料包括第一对准标记。 第一对准标记包括至少三个方向上的对准线。 半导体器件还包括第二材料，其包括第二对准标记。 第二对准标记对应于第一对准标记，使得当第二对准标记与第一对准标记对准时，第二材料与第一材料对准。

公开(公告)号：US08816415B2

公开(公告)日：2014-08-26

申请号：US13742747

申请日：2013-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Min Lin ,  Volume Chien ,  Chih-Kang Chao ,  Chi-Cherng Jeng ,  Pin Chia Su ,  Chih-Mu Huang

IPC: H01L31/062

CPC classification number: H01L31/02327 ,  H01L27/14629 ,  H01L31/0232 ,  H01L31/10 ,  H01L31/115 ,  H01L31/18

Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.

Abstract translation: 光电二极管结构包括设置在光电二极管下方的光电二极管和凹面反射器。 凹面反射器被布置成将来自上方的入射光反射到光电二极管。

公开(公告)号：US20220302110A1

公开(公告)日：2022-09-22

申请号：US17837046

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Jung Chen ,  I-Chih Chen ,  Chih-Mu Huang ,  Kai-Di Wu ,  Ming-Feng Lee ,  Ting-Chun Kuan

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.