公开(公告)号：US20240145380A1

公开(公告)日：2024-05-02

申请号：US18405117

申请日：2024-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76832

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

公开(公告)号：US11972975B2

公开(公告)日：2024-04-30

申请号：US17356959

申请日：2021-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chih-Wei Lu ,  Chung-Ju Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

摘要： A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

公开(公告)号：US11923293B2

公开(公告)日：2024-03-05

申请号：US17370107

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76832

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

公开(公告)号：US11842924B2

公开(公告)日：2023-12-12

申请号：US17337775

申请日：2021-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chih Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/5226

摘要： The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.

公开(公告)号：US11798910B2

公开(公告)日：2023-10-24

申请号：US17868946

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L24/48 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226

摘要： The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US11688782B2

公开(公告)日：2023-06-27

申请号：US17212476

申请日：2021-03-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure includes a gate structure over a substrate. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the source/drain epitaxial structure. The structure also includes a first via structure formed over the contact structure. The structure also includes a metal line electrically connected to the first via structure. The structure also includes a spacer layer formed over the sidewall and over a portion of a top surface of the metal line. The structure also includes a second via structure formed over the metal line through the spacer layer.

公开(公告)号：US20220392801A1

公开(公告)日：2022-12-08

申请号：US17337753

申请日：2021-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih Wei Lu ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L21/768 ,  H01L23/522

摘要： Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

公开(公告)号：US20220367361A1

公开(公告)日：2022-11-17

申请号：US17314294

申请日：2021-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L23/532 ,  H01L29/78 ,  H01L29/417 ,  H01L21/768

摘要： An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.

公开(公告)号：US12094823B2

公开(公告)日：2024-09-17

申请号：US17314294

申请日：2021-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao Liao ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Chung-Ju Lee

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L21/76885 ,  H01L29/41791 ,  H01L29/7851

摘要： An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.

公开(公告)号：US11942364B2

公开(公告)日：2024-03-26

申请号：US17868845

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L27/092

CPC分类号： H01L21/76831 ,  H01L21/76813 ,  H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7684 ,  H01L27/092

摘要： In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.