公开(公告)号：US09728581B2

公开(公告)日：2017-08-08

申请号：US14932949

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L29/78 ,  H01L29/82 ,  H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  H01L43/14

CPC classification number: H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US20170099711A1

公开(公告)日：2017-04-06

申请号：US15131831

申请日：2016-04-18

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Ajit Sharma ,  Srinath Ramaswamy ,  Sriram Narayanan

IPC: H05B33/08 ,  A61B5/1455 ,  A61B5/024

CPC classification number: H05B33/0818 ,  A61B5/02427 ,  A61B5/14551 ,  A61B5/7225 ,  Y02B20/346

Abstract: An LED (light-emitting diode) driver for a photoplethysmography system, including a switched-mode operational amplifier for driving a driver transistor with a source-drain path in series with the LED. In a first clock phase in which the LED is disconnected from the driver transistor, the amplifier is coupled in unity gain mode, and a sampling capacitor stores a voltage corresponding to the offset and flicker noise of the amplifier; the gate of the driver transistor is precharged to a reference voltage in this first clock phase. In a second clock phase, the sampled voltage at the capacitor is subtracted from the reference voltage applied to the amplifier input, so that the LED drive is adjusted according to the sampled noise. A signal from the transmitter channel is forwarded to a noise/ripple remover in the receiving channel, to remove transmitter noise from the received signal.

公开(公告)号：US09148159B1

公开(公告)日：2015-09-29

申请号：US14209813

申请日：2014-03-13

Applicant: Texas Instruments Incorporated

Inventor： Ajit Sharma ,  Seung Bae Lee ,  Srinath M. Ramaswamy ,  Sriram Narayanan ,  Arup Polley

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/36 ,  H03M1/44 ,  H03M1/00

CPC classification number: H03M1/0678 ,  H03M1/00 ,  H03M1/12 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

Abstract translation: 模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。 第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同的二进制算法迭代期间输出第二输出电压。 所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。

公开(公告)号：US20150263744A1

公开(公告)日：2015-09-17

申请号：US14209813

申请日：2014-03-13

Applicant: Texas Instruments Incorporated

Inventor： Ajit Sharma ,  Seung Bae Lee ,  Srinath M. Ramaswamy ,  Sriram Narayanan ,  Arup Polley

IPC: H03M1/06 ,  H03M1/36 ,  H03M1/44 ,  H03M1/12

CPC classification number: H03M1/0678 ,  H03M1/00 ,  H03M1/12 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

Abstract translation: 模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。 第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同二进制算法迭代期间输出第二输出电压。 所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。

公开(公告)号：US20190319068A1

公开(公告)日：2019-10-17

申请号：US16453468

申请日：2019-06-26

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/14 ,  H01L43/04 ,  H01L43/06

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US10396122B2

公开(公告)日：2019-08-27

申请号：US15639327

申请日：2017-06-30

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Rajni J. Aggarwal ,  Ajit Sharma

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

公开(公告)号：US10187940B2

公开(公告)日：2019-01-22

申请号：US15131831

申请日：2016-04-18

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Ajit Sharma ,  Srinath Ramaswamy ,  Sriram Narayanan

IPC: H05B33/08 ,  A61B5/024 ,  A61B5/1455 ,  A61B5/00

Abstract: An LED (light-emitting diode) driver for a photoplethysmography system, including a switched-mode operational amplifier for driving a driver transistor with a source-drain path in series with the LED. In a first clock phase in which the LED is disconnected from the driver transistor, the amplifier is coupled in unity gain mode, and a sampling capacitor stores a voltage corresponding to the offset and flicker noise of the amplifier; the gate of the driver transistor is precharged to a reference voltage in this first clock phase. In a second clock phase, the sampled voltage at the capacitor is subtracted from the reference voltage applied to the amplifier input, so that the LED drive is adjusted according to the sampled noise. A signal from the transmitter channel is forwarded to a noise/ripple remover in the receiving channel, to remove transmitter noise from the received signal.

公开(公告)号：US09667289B2

公开(公告)日：2017-05-30

申请号：US15084052

申请日：2016-03-29

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Ajit Sharma ,  Seung Bae Lee ,  Sriram Narayanan ,  Srinath Ramaswamy

IPC: H04L27/06 ,  H04B1/10

CPC classification number: H04B1/1036 ,  H04B1/0028 ,  H04B2001/1054

Abstract: Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.

公开(公告)号：US20160235313A1

公开(公告)日：2016-08-18

申请号：US14837179

申请日：2015-08-27

Applicant: Texas Instruments Incorporated

Inventor： Ajit Sharma ,  Sriram Narayanan ,  Srinath Mathur Ramaswamy ,  Arup Polley ,  Seung Bae Lee ,  Wen Li

IPC: A61B5/024 ,  A61B5/00

CPC classification number: A61B5/02427 ,  A61B5/6826 ,  A61B5/7228 ,  A61B2562/0238

Abstract: The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.

Abstract translation: 光接收器的电路减少环境直流分量和百分比直流分量，以便基本上只有一个良好的交流分量留下一个信号。 电路还提供增益控制，并且可以提供发射功率控制，以改变百分之AC组件的范围，以占据模数转换器的期望输入范围。

公开(公告)号：US08975963B2

公开(公告)日：2015-03-10

申请号：US13835264

申请日：2013-03-15

Applicant: Texas Instruments Incorporated

Inventor： Ajit Sharma ,  Kemal S. Demirci

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2203/45138 ,  H03F2203/45212 ,  H03F2203/45522 ,  H03F2203/45526

Abstract: A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based on the output signal, where the offset sensor includes a second amplifier configured to generate an offset reduction signal for the first amplifier based on the sensed DC offset. A T-network in the circuit includes at least three resistors coupled to provide a feedback connection between the input signal and the output signal for the first amplifier and to receive the offset reduction signal to mitigate DC offset in the first amplifier. Since this method reduces the low-frequency component of the signal, it also shapes and reduces the flicker noise.

Abstract translation: 电路包括被配置为放大输入信号以产生输出信号的第一放大器。 偏移传感器被配置为基于输出信号感测DC偏移，其中偏移传感器包括被配置为基于感测的DC偏移产生用于第一放大器的偏移减小信号的第二放大器。 电路中的T网络包括至少三个电阻器，其被耦合以在第一放大器的输入信号和输出信号之间提供反馈连接，并且接收偏移降低信号以减轻第一放大器中的DC偏移。 由于该方法降低了信号的低频分量，因此也可以形成和减少闪烁噪声。