公开(公告)号：US20220188121A1

公开(公告)日：2022-06-16

申请号：US17688260

申请日：2022-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20210326136A1

公开(公告)日：2021-10-21

申请号：US17360646

申请日：2021-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Duc BUI ,  Mel Alan PHIPPS ,  Todd T. HAHN

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

公开(公告)号：US20200371711A1

公开(公告)日：2020-11-26

申请号：US16422250

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR ,  Alan DAVIS

IPC: G06F3/06 ,  G06F9/30

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

公开(公告)号：US20200210198A1

公开(公告)日：2020-07-02

申请号：US16685747

申请日：2019-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38 ,  G06F9/48

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor, the method comprising detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20240036876A1

公开(公告)日：2024-02-01

申请号：US18487186

申请日：2023-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Duc BUI ,  Joseph ZBICIAK ,  Reid E. TATGE

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3838

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US20210390055A1

公开(公告)日：2021-12-16

申请号：US17462105

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK

IPC: G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

公开(公告)号：US20210326260A1

公开(公告)日：2021-10-21

申请号：US17364620

申请日：2021-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Timothy David ANDERSON ,  Joseph ZBICIAK ,  David E. SMITH ,  Matthew David PIERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

公开(公告)号：US20210157585A1

公开(公告)日：2021-05-27

申请号：US17164448

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20200371803A1

公开(公告)日：2020-11-26

申请号：US16421920

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

公开(公告)号：US20200050573A1

公开(公告)日：2020-02-13

申请号：US16545196

申请日：2019-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera BALASUBRAMANIAN ,  Joseph ZBICIAK ,  Sureshkumar GOVINDARAJ

IPC: G06F13/42 ,  G06F12/0875 ,  G06F15/78 ,  G06F9/38 ,  G06F9/30 ,  G06F15/76

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.