公开(公告)号：US20240184446A1

公开(公告)日：2024-06-06

申请号：US18441279

申请日：2024-02-14

Applicant: Texas Instruments Incorporated

Inventor： Kai CHIRCA ,  Daniel WU ,  Matthew David PIERSON

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27

CPC classification number: G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

Abstract: Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

公开(公告)号：US20220374356A1

公开(公告)日：2022-11-24

申请号：US17875424

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David PIERSON ,  Kai CHIRCA ,  Daniel WU

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.

公开(公告)号：US20230325078A1

公开(公告)日：2023-10-12

申请号：US18332831

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David PIERSON ,  Daniel WU ,  Kai CHIRCA

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F3/0604 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4027 ,  G06F12/0855 ,  G06F12/0607 ,  G06F12/0828 ,  G06F12/0831 ,  G06F13/124 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0857 ,  G06F13/1663 ,  G06F3/0632 ,  G06F3/0673 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F9/30101 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F13/1642 ,  G06F3/064 ,  G06F9/30123 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/657 ,  G06F2212/304 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1016 ,  G06F12/0846

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

公开(公告)号：US20200117618A1

公开(公告)日：2020-04-16

申请号：US16653378

申请日：2019-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David PIERSON ,  Daniel WU ,  Kai CHIRCA

IPC: G06F13/16

Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

公开(公告)号：US20250060873A1

公开(公告)日：2025-02-20

申请号：US18939018

申请日：2024-11-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Matthew David PIERSON

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

公开(公告)号：US20230384931A1

公开(公告)日：2023-11-30

申请号：US18229814

申请日：2023-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Matthew David PIERSON

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F3/0604 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4027 ,  G06F12/0855 ,  G06F12/0607 ,  G06F12/0828 ,  G06F12/0831 ,  G06F13/124 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0857 ,  G06F13/1663 ,  G06F3/0632 ,  G06F3/0673 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F9/30101 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F13/1642 ,  G06F3/064 ,  G06F9/30123 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/657 ,  G06F2212/304 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1016 ,  G06F12/0846

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

公开(公告)号：US20220283942A1

公开(公告)日：2022-09-08

申请号：US17749921

申请日：2022-05-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Daniel WU ,  Matthew David PIERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

公开(公告)号：US20220229779A1

公开(公告)日：2022-07-21

申请号：US17715022

申请日：2022-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Matthew David PIERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

公开(公告)号：US20210326260A1

公开(公告)日：2021-10-21

申请号：US17364620

申请日：2021-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Timothy David ANDERSON ,  Joseph ZBICIAK ,  David E. SMITH ,  Matthew David PIERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

公开(公告)号：US20220374357A1

公开(公告)日：2022-11-24

申请号：US17875440

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Matthew David PIERSON ,  Kai CHIRCA ,  Timothy David ANDERSON

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.