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公开(公告)号：US20160351247A1
公开(公告)日：2016-12-01
申请号：US15236797
申请日：2016-08-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prajkta Vyavahare , Rajat Chauhan , Siva Srinivas Kothamasu
IPC: G11C11/4093 , G11C11/4074 , G06F13/10 , G11C11/4094
CPC classification number: G11C11/4093 , G06F1/3296 , G06F13/102 , G11C7/1057 , G11C11/4074 , G11C11/4094 , H03K17/687 , Y02D10/14
Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.
Abstract translation: 本公开提供了由输入/输出（IO）电源电压供电的输入/输出（IO）电路。 IO电路包括接收第一反相信号，IO电源电压，偏置电压和焊盘电压的截止电路。 输出级与断路电路相连。 输出级接收第一信号，第二信号和偏置电压。 焊盘耦合到输出级，并且在焊盘处产生的电压是焊盘电压。 当IO电源电压转换低于定义的阈值时，截止电路和输出级将焊盘电压保持在逻辑高电平。
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公开(公告)号：US12164323B2
公开(公告)日：2024-12-10
申请号：US17833474
申请日：2022-06-06
Applicant: Texas Instruments Incorporated
Inventor： Rajat Chauhan , Sundeep Lakshmana Javvaji
IPC: G05F3/26
Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. An output transistor is coupled to the first stage and to the current mirror circuit. A voltage divider network is coupled to the output transistor, and a power source is coupled to the second stage and to the voltage divider network.
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公开(公告)号：US20230343375A1
公开(公告)日：2023-10-26
申请号：US18203806
申请日：2023-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur , Rishav Gupta
IPC: G11C7/10 , H03K19/007
CPC classification number: G11C7/1084 , H03K19/007
Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.
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公开(公告)号：US11705169B2
公开(公告)日：2023-07-18
申请号：US17537872
申请日：2021-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur , Rishav Gupta
IPC: G11C7/10 , H03K19/007
CPC classification number: G11C7/1084 , H03K19/007
Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.
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公开(公告)号：US20220390976A1
公开(公告)日：2022-12-08
申请号：US17682811
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur
Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.
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Patent Agency Ranking
公开(公告)号：US11293954B2
公开(公告)日：2022-04-05
申请号：US16363779
申请日：2019-03-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naman Gupta , Rajat Chauhan , Santhosh Kumar Srinivasan
IPC: G01R19/165 , G01R31/382 , G05F3/26 , H03K3/037
Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.
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公开(公告)号：US10855184B2
公开(公告)日：2020-12-01
申请号：US16601143
申请日：2019-10-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vinod Joseph Menezes , Manikandan Rr , Rajat Chauhan , Vipul Kumar Singhal , Mahesh Madhukar Mehendale , Kaichien Tsai
Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.
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公开(公告)号：US12131799B2
公开(公告)日：2024-10-29
申请号：US18203806
申请日：2023-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur , Rishav Gupta
IPC: G11C7/10 , H03K19/007
CPC classification number: G11C7/1084 , H03K19/007
Abstract: A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.
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公开(公告)号：US11852663B2
公开(公告)日：2023-12-26
申请号：US17824505
申请日：2022-05-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Danielle Griffith , Per Torstein Roine , James Murdock , Bernhard Ruck
IPC: G01R19/257 , H03M1/66 , G01R31/3835
CPC classification number: G01R19/257 , G01R31/3835 , H03M1/66
Abstract: One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.
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公开(公告)号：US11755046B2
公开(公告)日：2023-09-12
申请号：US17353387
申请日：2021-06-21
Applicant: Texas Instruments Incorporated
Inventor： Jayateerth Pandurang Mathad , Rajat Chauhan
Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.
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