公开(公告)号：US10790228B2

公开(公告)日：2020-09-29

申请号：US16372455

申请日：2019-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L21/288 ,  H01L23/367 ,  H01L23/373 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/48

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US20180151487A1

公开(公告)日：2018-05-31

申请号：US15361401

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/288 ,  H01L21/285 ,  H01L21/324 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53209 ,  H01L23/53276

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US20160293834A1

公开(公告)日：2016-10-06

申请号：US14676233

申请日：2015-04-01

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Archana Venugopal ,  Robert Reid Doering ,  Luigi Colombo

IPC: H01L43/10 ,  G01R33/07 ,  H01L43/06

CPC classification number: H01L43/10 ,  G01R33/07 ,  H01L43/065

Abstract: Described examples include graphene Hall sensors, magnetic sensor systems and methods for sensing a magnetic field using an adjustable gate voltage to adapt the Hall sensor magnetic field sensitivity according to a control input for environmental or process compensation and/or real-time adaptation for balancing power consumption and minimum detectable field performance. The graphene Hall sensor gate voltage can be modulated and the sensor output signal can be demodulated to combat flicker or other low frequency noise. Also, graphene Hall sensors can be provided with capacitive coupled contacts for reliable low impedance AC coupling to instrumentation amplifiers or other circuits using integral capacitance.

Abstract translation: 所描述的实例包括石墨烯霍尔传感器，磁传感器系统和用于使用可调节栅极电压感测磁场的方法，以根据用于环境或过程补偿的控制输入和/或用于平衡功率的实时适应来适应霍尔传感器的磁场灵敏度 消耗和最小可检测现场性能。 可以对石墨烯霍尔传感器门电压进行调制，并且传感器输出信号可被解调，以防止闪烁或其他低频噪声。 此外，石墨烯霍尔传感器可以提供电容耦合触点，用于可靠的低阻抗交流耦合到仪表放大器或使用积分电容的其他电路。

公开(公告)号：US20230307312A1

公开(公告)日：2023-09-28

申请号：US18143446

申请日：2023-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L23/3733 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US11676880B2

公开(公告)日：2023-06-13

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3733 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20210118762A1

公开(公告)日：2021-04-22

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US10811334B2

公开(公告)日：2020-10-20

申请号：US15361394

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US10181521B2

公开(公告)日：2019-01-15

申请号：US15437818

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/778 ,  H01L23/66 ,  H01L49/02

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

公开(公告)号：US20180240886A1

公开(公告)日：2018-08-23

申请号：US15437818

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L29/66045 ,  H01L23/66 ,  H01L28/40 ,  H01L29/1606 ,  H01L29/778 ,  H01L2223/6677

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

公开(公告)号：US20180151464A1

公开(公告)日：2018-05-31

申请号：US15361397

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/528 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.