公开(公告)号：US20190154755A1

公开(公告)日：2019-05-23

申请号：US16247271

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/28 ,  G01R1/04 ,  G01R1/067 ,  G01R31/3185

Abstract: In a method of testing a semiconductor wafer including a scribe line and multiple dies, the method includes implementing a first landing pad on the scribe line, and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip, and applying an ATE resource to the first cluster of dies.

公开(公告)号：US10180454B2

公开(公告)日：2019-01-15

申请号：US15130429

申请日：2016-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Mahesh M. Mehendale ,  Vinod Menezes ,  Vipul K. Singhal

IPC: G01R31/26 ,  G01R31/28 ,  G01R1/067 ,  G01R31/3185 ,  G01R1/04

Abstract: A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.

公开(公告)号：US09263147B2

公开(公告)日：2016-02-16

申请号：US14490170

申请日：2014-09-18

Applicant: Texas Instruments Incorporated

Inventor： Rajat Mehrotra ,  Rubin Ajit Parekhji ,  Maheedhar Jalasutram ,  Charu Shrimali

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C29/12 ,  G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3422 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C29/12 ,  G11C29/26 ,  G11C29/4401 ,  G11C2029/2602

Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.

Abstract translation: 用于一组闪速存储器组装置的并发测试的装置包括耦合到测试控制器的存储器数据路径（MDP）模块。 MDP模块包括测试控制模块，其被配置为生成并发控制信号，其配置要同时测试的闪存组集合; 以及一组比较器，其响应于并发控制信号和来自闪存组的输入而产生第一比较器输出。 还原逻辑被配置为生成还原逻辑输出，其组合要压缩的比较器输出的状态。 控制逻辑被配置用于跨越闪存组的不同闪存位的选择性编程。 如果在任何访问中从闪存组中读取的数据不匹配，则失败标志被配置为产生输出值“0”，并且如果在任何访问中读取的数据不匹配，则输出值1 。