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公开(公告)号：US11162986B2
公开(公告)日：2021-11-02
申请号：US16597612
申请日：2019-10-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.
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公开(公告)号：USRE48613E1
公开(公告)日：2021-06-29
申请号：US16503240
申请日：2019-07-03
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.
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公开(公告)号：US10101438B2
公开(公告)日：2018-10-16
申请号：US14687617
申请日：2015-04-15
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Karthik Ramasubramanian , Sriram Murali , Sreekiran Samala , Krishnanshu Dandu
Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.
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公开(公告)号：US09515667B2
公开(公告)日：2016-12-06
申请号：US14587951
申请日：2014-12-31
Applicant: Texas Instruments Incorporated
Inventor： Sreekiran Samala , Vineet Mishra , Mahadevan Shankara Venkiteswaran
CPC classification number: H03L7/0995 , H03B5/24 , H03K3/0231 , H03L1/026 , H03L7/095 , H03L7/099 , H03L7/104 , H03L7/18
Abstract: Circuitry for providing an oscillating output signal. The circuitry comprises a transconductance circuit having a first input, a second input, and an output. The circuitry further comprises an oscillator circuit coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Also included are circuitry for providing a first voltage to the first input of the transconductance circuit and a frequency controlled circuit for providing a second voltage to the second input the transconductance circuit. The second voltage is response to a frequency of operation of the frequency controlled circuit, and the frequency of operation of the frequency controlled circuit is responsive to feedback from the output of the oscillator circuit.
Abstract translation: 提供振荡输出信号的电路。 电路包括具有第一输入，第二输入和输出的跨导电路。 电路还包括耦合以从跨导电路的输出接收电压的振荡器电路，其中振荡输出信号响应振荡器电路的输出。 还包括用于向跨导电路的第一输入提供第一电压的电路和用于向第二输入提供跨导电路的第二电压的频率控制电路。 第二电压响应于频率控制电路的工作频率，频率控制电路的工作频率响应于来自振荡器电路的输出的反馈。
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公开(公告)号：US11789137B2
公开(公告)日：2023-10-17
申请号：US17138549
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Indu Prathapan
CPC classification number: G01S13/345 , G01S7/032 , G01S7/352 , H03C3/0925 , H03L7/087 , H03L7/099
Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.
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Patent Agency Ranking
公开(公告)号：US11747436B2
公开(公告)日：2023-09-05
申请号：US17020931
申请日：2020-09-15
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Karthik Ramasubramanian , Sriram Murali , Sreekiran Samala , Krishnanshu Dandu
IPC: G01S7/292 , G01S13/88 , G01S13/00 , G01S7/35 , G01S13/34 , G01S7/03 , G01S7/02 , G01S7/41 , G01S13/04
CPC classification number: G01S7/292 , G01S7/023 , G01S7/038 , G01S7/354 , G01S7/414 , G01S13/003 , G01S13/343 , G01S13/88 , G01S7/356 , G01S7/358 , G01S13/04
Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.
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公开(公告)号：US11486916B2
公开(公告)日：2022-11-01
申请号：US17515637
申请日：2021-11-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.
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公开(公告)号：US20210011118A1
公开(公告)日：2021-01-14
申请号：US17020931
申请日：2020-09-15
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Karthik Ramasubramanian , Sriram Murali , Sreekiran Samala , Krishnanshu Dandu
Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.
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19.发明授权公开(公告)号：US10746851B2
公开(公告)日：2020-08-18
申请号：US14975416
申请日：2015-12-18
Applicant: Texas Instruments Incorporated
Abstract: A testing device for FMCW radar includes an input for receiving a chirp signal generated by the radar. An IQ down-converter coupled to the input down-converts the chirp signal. A digitizer extracts digitized IQ signals from the down-converted chirp signal. A processor coupled to the digitizer determines at least one of frequency linearity and phase noise of the chirp signal.
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公开(公告)号：US10481187B2
公开(公告)日：2019-11-19
申请号：US14588014
申请日：2014-12-31
Applicant: Texas Instruments Incorporated
Inventor： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.
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