-
公开(公告)号:US20180277744A1
公开(公告)日:2018-09-27
申请号:US15702403
申请日:2017-09-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Masaru TOKO , Keiji HOSOTANI , Hisanori AIKAWA , Tatsuya KISHI
CPC classification number: H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).
-
公开(公告)号:US20180277183A1
公开(公告)日:2018-09-27
申请号:US15702430
申请日:2017-09-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji HOSOTANI , Tatsuya KISHI , Akira KATAYAMA
CPC classification number: G11C11/161 , G11C11/1673 , H01L27/228 , H01L43/08 , H01L43/10
Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.
-
公开(公告)号:US20180277743A1
公开(公告)日:2018-09-27
申请号:US15702339
申请日:2017-09-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Tsuneo INABA , Tatsuya KISHI , Masahiko NAKAYAMA
CPC classification number: H01L43/02 , G11C7/1096 , G11C11/1675 , G11C11/1697 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
-
-