公开(公告)号：US20180102156A1

公开(公告)日：2018-04-12

申请号：US15835988

申请日：2017-12-08

Applicant: TOSHIBA MEMORY CORPORATION ,  SK HYNIX INC.

Inventor： Hisanori AIKAWA ,  Tatsuya KISHI ,  Keisuke NAKATSUKA ,  Satoshi INABA ,  Masaru TOKO ,  Keiji HOSOTANI ,  Jae Yun YI ,  Hong Ju SUH ,  Se Dong KIM

IPC: G11C11/16 ,  G11C5/06

CPC classification number: G11C11/1673 ,  G11C5/063 ,  G11C8/08 ,  G11C8/12 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16 ,  H01L45/1675

Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

公开(公告)号：US20190288184A1

公开(公告)日：2019-09-19

申请号：US16129265

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya KISHI ,  Youngmin EEH ,  Kazuya SAWADA ,  Masaru TOKO

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01L27/22

Abstract: According to one embodiment, a magnetic memory device includes a stacked structure that includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein the entire first magnetic layer exhibits a parallel or antiparallel magnetization direction to the second magnetic layer, and has an anisotropic magnetic field Hk_film within a range from −1 kOe to +1 kOe.

公开(公告)号：US20190259438A1

公开(公告)日：2019-08-22

申请号：US16400048

申请日：2019-05-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya KISHI ,  Tsuneo INABA ,  Daisuke WATANABE ,  Masahiko NAKAYAMA ,  Nobuyuki OGATA ,  Masaru TOKO ,  Hisanori AIKAWA ,  Jyunichi OZEKI ,  Toshihiko NAGASE ,  Young Min EEH ,  Kazuya SAWADA

IPC: G11C11/16 ,  G11C7/10

Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.

公开(公告)号：US20180075895A1

公开(公告)日：2018-03-15

申请号：US15456031

申请日：2017-03-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tatsuya KISHI ,  Tsuneo INABA ,  Daisuke WATANABE ,  Masahiko NAKAYAMA ,  Nobuyuki OGATA ,  Masaru TOKO ,  Hisanori AIKAWA ,  Jyunichi OZEKI ,  Toshihiko NAGASE ,  Young Min EEH ,  Kazuya SAWADA

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/1096 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.

公开(公告)号：US20180277744A1

公开(公告)日：2018-09-27

申请号：US15702403

申请日：2017-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaru TOKO ,  Keiji HOSOTANI ,  Hisanori AIKAWA ,  Tatsuya KISHI

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).