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公开(公告)号：US20200091227A1
公开(公告)日：2020-03-19
申请号：US16353069
申请日：2019-03-14
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Masayoshi IWAYAMA , Tatsuya KISHI , Masahiko NAKAYAMA , Toshihiko NAGASE , Daisuke WATANABE , Tadashi KAI
Abstract: According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses.
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公开(公告)号：US20190259438A1
公开(公告)日：2019-08-22
申请号：US16400048
申请日：2019-05-01
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Tatsuya KISHI , Tsuneo INABA , Daisuke WATANABE , Masahiko NAKAYAMA , Nobuyuki OGATA , Masaru TOKO , Hisanori AIKAWA , Jyunichi OZEKI , Toshihiko NAGASE , Young Min EEH , Kazuya SAWADA
Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.
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公开(公告)号：US20180075895A1
公开(公告)日：2018-03-15
申请号：US15456031
申请日：2017-03-10
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Tatsuya KISHI , Tsuneo INABA , Daisuke WATANABE , Masahiko NAKAYAMA , Nobuyuki OGATA , Masaru TOKO , Hisanori AIKAWA , Jyunichi OZEKI , Toshihiko NAGASE , Young Min EEH , Kazuya SAWADA
IPC: G11C11/16
CPC classification number: G11C11/1675 , G11C7/1096 , G11C11/1655 , G11C11/1657 , G11C11/1673
Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.
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公开(公告)号：US20210335888A1
公开(公告)日：2021-10-28
申请号：US17371138
申请日：2021-07-09
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Masayoshi IWAYAMA , Tatsuya KISHI , Masahiko NAKAYAMA , Toshihiko NAGASE , Daisuke WATANABE , Tadashi KAI
Abstract: A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.
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公开(公告)号：US20210210549A1
公开(公告)日：2021-07-08
申请号：US17206364
申请日：2021-03-19
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Masahiko NAKAYAMA , Kazumasa SUNOUCHI , Gaku SUDO , Tadashi KAI
Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
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Patent Agency Ranking
公开(公告)号：US20200302984A1
公开(公告)日：2020-09-24
申请号：US16557802
申请日：2019-08-30
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Tadashi KAI , Masahiko NAKAYAMA , Jyunichi OZEKI , Shogo ITAI
Abstract: According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.
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公开(公告)号：US20200075671A1
公开(公告)日：2020-03-05
申请号：US16678316
申请日：2019-11-08
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Jyunichi OZEKI , Masahiko NAKAYAMA , Hiroaki YODA , Eiji KITAGAWA , Takao OCHIAI , Minoru AMANO , Kenji NOMA
Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, and including a first main surface and a second main surface located opposite to the first main surface, a second magnetic layer provided on a first main surface side of the first magnetic layer, and having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein a saturation magnetization of a part of the first magnetic layer which is located close to the first main surface is higher than a saturation magnetization of a part of the first magnetic layer which is located close to the second main surface.
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公开(公告)号：US20200303455A1
公开(公告)日：2020-09-24
申请号：US16559254
申请日：2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Masahiko NAKAYAMA , Toshihiko NAGASE , Tomomi FUNAYAMA , Hironobu FURUHASHI , Kazumasa SUNOUCHI
Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
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公开(公告)号：US20200303453A1
公开(公告)日：2020-09-24
申请号：US16559162
申请日：2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Masahiko NAKAYAMA , Kazumasa SUNOUCHI , Gaku SUDO , Tadashi KAI
Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
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公开(公告)号：US20180277743A1
公开(公告)日：2018-09-27
申请号：US15702339
申请日：2017-09-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Tsuneo INABA , Tatsuya KISHI , Masahiko NAKAYAMA
CPC classification number: H01L43/02 , G11C7/1096 , G11C11/1675 , G11C11/1697 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
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