公开(公告)号：US08253465B2

公开(公告)日：2012-08-28

申请号：US13186366

申请日：2011-07-19

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K3/00 ,  H03K5/13 ,  H03H11/16

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

摘要翻译： 半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及 检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位 响应于控制信号。

公开(公告)号：US07961026B2

公开(公告)日：2011-06-14

申请号：US12003676

申请日：2007-12-31

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

摘要翻译： 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

公开(公告)号：US07884647B2

公开(公告)日：2011-02-08

申请号：US12326990

申请日：2008-12-03

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

摘要翻译： 提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制 信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

公开(公告)号：US20090273493A1

公开(公告)日：2009-11-05

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20090121701A1

公开(公告)日：2009-05-14

申请号：US12266693

申请日：2008-11-07

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147

摘要： A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

摘要翻译： 带隙参考产生电路包括：运算放大器，被配置为产生带隙参考电压; 以及增益控制器，被配置为在正常模式和低功率模式下以不同的值来控制运算放大器的增益。

公开(公告)号：US07952413B2

公开(公告)日：2011-05-31

申请号：US12795132

申请日：2010-06-07

申请人： Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G06F1/06

CPC分类号： G06F1/06

摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.

摘要翻译： 一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位 接收脉冲信号对的相位时钟发生单元。

公开(公告)号：US07876148B2

公开(公告)日：2011-01-25

申请号：US12344552

申请日：2008-12-28

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/093 ,  H03L7/095

CPC分类号： H03L7/095 ,  G01R29/0273 ,  H03K5/153 ,  H03K2005/00065 ,  H03K2005/00071 ,  Y10S331/02

摘要： A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.

摘要翻译： 低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元，被配置为对驱动器单元的输出电压进行充电的充电/放电单元，被配置为比较充电/放电的输出电压 具有参考值的单元以输出方波信号;以及切换单元，被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

公开(公告)号：US07855933B2

公开(公告)日：2010-12-21

申请号：US12165045

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K2005/00208 ,  H03L7/0805 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/24

摘要： A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

摘要翻译： 一种具有时钟同步电路的半导体存储器件，其能够执行期望的相位/频率锁定操作，而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。 该装置包括锁相环，其检测反馈时钟信号和参考时钟信号之间的相位/频率差，以产生对应于检测到的相位/频率差的振荡控制电压信号，并产生对应于 振荡控制电压信号。 注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率，并产生与参考时钟信号同步的内部时钟信号。

公开(公告)号：US07796064B2

公开(公告)日：2010-09-14

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20090279378A1

公开(公告)日：2009-11-12

申请号：US12164797

申请日：2008-06-30

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

摘要翻译： 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。