公开(公告)号：US12136644B2

公开(公告)日：2024-11-05

申请号：US18063339

申请日：2022-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/522 ,  H01L21/311 ,  H01L49/02

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US11742204B2

公开(公告)日：2023-08-29

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20210288009A1

公开(公告)日：2021-09-16

申请号：US17333187

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.