公开(公告)号：US20230369049A1

公开(公告)日：2023-11-16

申请号：US18350583

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/31058 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/0273

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20240379584A1

公开(公告)日：2024-11-14

申请号：US18780104

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L21/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US11851321B2

公开(公告)日：2023-12-26

申请号：US17188933

申请日：2021-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Li Yang ,  Kai-Di Wu ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Cheng Jen Lin ,  Chin Wei Kang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81C1/0069 ,  B81B2203/019 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/0181 ,  B81C2203/032 ,  B81C2203/0735

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

公开(公告)号：US20210351139A1

公开(公告)日：2021-11-11

申请号：US17385205

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Tseng ,  Yu-Feng Chen ,  Cheng Jen Lin ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Kuo-Ching Hsu ,  Hong-Seng Shue ,  Ming-Hong Cha ,  Chao-Yi Wang ,  Mirng-Ji Lii

IPC: H01L23/58 ,  H01L23/31 ,  H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L23/522

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

公开(公告)号：US20210265165A1

公开(公告)日：2021-08-26

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20210151550A1

公开(公告)日：2021-05-20

申请号：US17140766

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L49/02 ,  H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US12230595B2

公开(公告)日：2025-02-18

申请号：US17333187

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/488

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US20240371915A1

公开(公告)日：2024-11-07

申请号：US18777699

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US11532692B2

公开(公告)日：2022-12-20

申请号：US17140766

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/311 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US20250149485A1

公开(公告)日：2025-05-08

申请号：US19013241

申请日：2025-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/488 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.