公开(公告)号：US20200273827A1

公开(公告)日：2020-08-27

申请号：US16871032

申请日：2020-05-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hsiung Lu ,  Chen-Shien Chen ,  Chen-En Yen ,  Cheng-Jen Lin ,  Chin-Wei Kang ,  Kai-Jun Zhan

IPC分类号： H01L23/00

摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

公开(公告)号：US10651142B2

公开(公告)日：2020-05-12

申请号：US16403631

申请日：2019-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hsiung Lu ,  Chen-Shien Chen ,  Chen-En Yen ,  Cheng-Jen Lin ,  Chin-Wei Kang ,  Kai-Jun Zhan

IPC分类号： H01L23/52 ,  H01L23/00

摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

公开(公告)号：US10283471B1

公开(公告)日：2019-05-07

申请号：US15841336

申请日：2017-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hsiung Lu ,  Chen-Shien Chen ,  Chen-En Yen ,  Cheng-Jen Lin ,  Chin-Wei Kang ,  Kai-Jun Zhan

IPC分类号： H01L23/52 ,  H01L23/00

摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

公开(公告)号：US20240021499A1

公开(公告)日：2024-01-18

申请号：US18362559

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC分类号： H01L23/48 ,  H01L23/60 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L23/60 ,  H01L21/76877 ,  H01L21/76898

摘要： Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

公开(公告)号：US11776881B2

公开(公告)日：2023-10-03

申请号：US17704762

申请日：2022-03-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC分类号： H01L23/48 ,  H01L23/60 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/60

摘要： A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

公开(公告)号：US20220216133A1

公开(公告)日：2022-07-07

申请号：US17704762

申请日：2022-03-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsu-Lun Liu ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chen-En Yen ,  Cheng-Lung Yang ,  Kuanchih Huang

IPC分类号： H01L23/48 ,  H01L23/60 ,  H01L21/768

摘要： A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.

公开(公告)号：US20210265165A1

公开(公告)日：2021-08-26

申请号：US17316008

申请日：2021-05-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

摘要： A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20230369049A1

公开(公告)日：2023-11-16

申请号：US18350583

申请日：2023-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/31058 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/0273

摘要： A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US11152319B2

公开(公告)日：2021-10-19

申请号：US16871032

申请日：2020-05-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Hsiung Lu ,  Chen-Shien Chen ,  Chen-En Yen ,  Cheng-Jen Lin ,  Chin-Wei Kang ,  Kai-Jun Zhan

IPC分类号： H01L23/52 ,  H01L23/00

摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.

公开(公告)号：US11101233B1

公开(公告)日：2021-08-24

申请号：US16868909

申请日：2020-05-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-En Yen ,  Chin-Wei Kang ,  Kai-Jun Zhan ,  Wen-Hsiung Lu ,  Cheng-Jen Lin ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC分类号： H01L21/48 ,  H01L23/552 ,  H01L23/00

摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.