公开(公告)号：US11817491B2

公开(公告)日：2023-11-14

申请号：US16935061

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0653

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

公开(公告)号：US11810917B2

公开(公告)日：2023-11-07

申请号：US17733169

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US20230260897A1

公开(公告)日：2023-08-17

申请号：US18301757

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

公开(公告)号：US20230238319A1

公开(公告)日：2023-07-27

申请号：US18195000

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/0886

Abstract: A semiconductor structure (MG) includes a metal gate structure disposed over a semiconductor substrate, a dielectric layer disposed adjacent to the MG, a source/drain (S/D) feature disposed adjacent to the dielectric layer, and a S/D contact disposed over the S/D feature. The S/D contact includes a first metal layer disposed over the S/D feature and a second metal layer disposed on the first metal layer.

公开(公告)号：US11688691B2

公开(公告)日：2023-06-27

申请号：US17164449

申请日：2021-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Wayne Lai

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/785 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US11670581B2

公开(公告)日：2023-06-06

申请号：US17104760

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53204 ,  H01L23/53209 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a source/drain (S/D) feature formed in an interlayer dielectric layer (ILD), a S/D contact via electrically connected to the S/D feature, a metal feature formed over the S/D contact via, and a metal line formed over the metal feature and electrically connected to the S/D contact via. The metal line is formed of a material different from that of the S/D contact via, and the S/D contact via is spaced apart from the metal line. By providing the metal feature, electromigration between the metal line and the contact via may be advantageously reduced or substantially eliminated.

公开(公告)号：US20230121408A1

公开(公告)日：2023-04-20

申请号：US18066071

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L23/532

Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

公开(公告)号：US11621224B2

公开(公告)日：2023-04-04

申请号：US16583697

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor structure includes a metal gate structure (MG) disposed over a semiconductor substrate, gate spacers disposed on sidewalls of the MG, and a gate contact disposed on the MG. The semiconductor structure further includes an etch-stop layer (ESL) disposed on the gate spacers, and a source/drain (S/D) contact disposed adjacent to the gate spacers, where a top portion of the S/D contact defined by the ESL is narrower than a bottom portion of the S/D contact defined by the gate spacers.

公开(公告)号：US11594602B2

公开(公告)日：2023-02-28

申请号：US16850267

申请日：2020-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US11563001B2

公开(公告)日：2023-01-24

申请号：US17006167

申请日：2020-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Chiao-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.