公开(公告)号：US10515977B2

公开(公告)日：2019-12-24

申请号：US16033357

申请日：2018-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.

公开(公告)号：US20190148389A1

公开(公告)日：2019-05-16

申请号：US16022702

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/40 ,  H01L21/765 ,  H01L23/00

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US20170345832A1

公开(公告)日：2017-11-30

申请号：US15162761

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11521 ,  H01L21/823828 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7831

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes comprise polysilicon. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

公开(公告)号：US09812460B1

公开(公告)日：2017-11-07

申请号：US15162761

申请日：2016-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/823828 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7831

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes comprise polysilicon. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

公开(公告)号：US20160233228A1

公开(公告)日：2016-08-11

申请号：US14645993

申请日：2015-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332

Abstract: The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes, and an associated method of fabrication. In some embodiments, the non-planar FEOL capacitor has a first electrode disposed over a substrate. A charge trapping dielectric layer is disposed onto the substrate at a position adjacent to the first electrode. The charge trapping dielectric layer has an “L” shape, with a lateral component extending in a first direction and a vertical component extending in a second direction. A second electrode is arranged onto the lateral component and is separated from the first electrode by the first component.

Abstract translation: 本公开涉及一种包括设置在电极之间的电荷捕获介电层的非平面FEOL（前端线）电容器和相关的制造方法。 在一些实施例中，非平面FEOL电容器具有设置在衬底上的第一电极。 电荷捕获电介质层在与第一电极相邻的位置处设置在基板上。 电荷俘获介电层具有“L”形状，其中侧向分量沿第一方向延伸，垂直分量沿第二方向延伸。 第二电极布置在侧向部件上并且通过第一部件与第一电极分离。

公开(公告)号：US11424263B2

公开(公告)日：2022-08-23

申请号：US16695475

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L29/06 ,  H01L21/76 ,  H01L27/11573 ,  H01L21/762 ,  H01L27/11565

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.

公开(公告)号：US20200098777A1

公开(公告)日：2020-03-26

申请号：US16695475

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L21/762 ,  H01L27/11573 ,  H01L21/76 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.

公开(公告)号：US10276587B2

公开(公告)日：2019-04-30

申请号：US15167070

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11573 ,  H01L29/423 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11536

Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.

公开(公告)号：US09947676B2

公开(公告)日：2018-04-17

申请号：US15205221

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521 ,  H01L27/11526

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7883

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer. The select gate electrodes or the control gate electrodes comprise metal and have bottom and sidewall surfaces covered by the high-k gate dielectric layer.

公开(公告)号：US20180012898A1

公开(公告)日：2018-01-11

申请号：US15205221

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7883

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer. The select gate electrodes or the control gate electrodes comprise metal and have bottom and sidewall surfaces covered by the high-k gate dielectric layer.