公开(公告)号：US11610825B2

公开(公告)日：2023-03-21

申请号：US17080348

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fen Chen ,  Tsung-Ying Liu ,  Yeh-Hsun Fang ,  Bang-Yu Huang ,  Chui-Ya Peng

IPC: H01L21/02 ,  H01L21/66 ,  C30B29/06 ,  C30B25/16 ,  C23C16/02 ,  H01L21/306 ,  C23C16/52 ,  C23C16/24 ,  C30B25/18

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

公开(公告)号：US11411108B2

公开(公告)日：2022-08-09

申请号：US17078856

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

公开(公告)号：US20200098650A1

公开(公告)日：2020-03-26

申请号：US16696890

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fen Chen ,  Tsung-Ying Liu ,  Yeh-Hsun Fang ,  Bang-Yu Huang ,  Chui-Ya Peng

IPC: H01L21/66 ,  C30B29/06 ,  C30B25/16 ,  C23C16/02 ,  H01L21/306 ,  C23C16/52 ,  C23C16/24 ,  C30B25/18

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

公开(公告)号：US10515861B2

公开(公告)日：2019-12-24

申请号：US15940357

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fen Chen ,  Tsung-Ying Liu ,  Yeh-Hsun Fang ,  Bang-Yu Huang ,  Chui-Ya Peng

IPC: H01L21/02 ,  H01L21/66 ,  C30B29/06 ,  C30B25/16 ,  C23C16/02 ,  H01L21/306 ,  C23C16/52 ,  C23C16/24

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

公开(公告)号：US09978634B2

公开(公告)日：2018-05-22

申请号：US14632690

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsu Yen ,  Bang-Yu Huang ,  Chui-Ya Peng ,  Ching-Wen Chen

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  C23C16/04 ,  C23C16/505

CPC classification number: H01L21/76224 ,  C23C16/045 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/0649

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

公开(公告)号：US20150048475A1

公开(公告)日：2015-02-19

申请号：US13967558

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yeu Tsai ,  Chia-Hui Lin ,  Ching-Yu Chen ,  Chui-Ya Peng

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229

Abstract: A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.

Abstract translation: 公开了一种包括以下概述的操作的方法。 绝缘材料设置在半导体衬底上并在半导体衬底之上的多个沟槽内。 第一层形成在绝缘材料上。 去除第一层和绝缘材料。

公开(公告)号：US12198953B2

公开(公告)日：2025-01-14

申请号：US18338981

申请日：2023-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Rong Xiao ,  Wei-Hsiang Huang ,  Sen-Yeo Peng ,  Chui-Ya Peng

IPC: H01L21/67

Abstract: A system includes a cooler, a concentration meter, a first pump and a second pump. The cooler is configured to cool first liquid by second liquid in the cooler. The concentration meter is configured to measure a concentration of the first liquid. The first pump is configured to move the first liquid according to the concentration. The second pump is coupled to the cooler, disposed with the first pump in a parallel manner, and configured to move the second liquid.

公开(公告)号：US11527380B2

公开(公告)日：2022-12-13

申请号：US16837724

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Meng ,  Chui-Ya Peng ,  Shih-Hao Lin

IPC: H01J37/32 ,  H01J37/317 ,  H01J37/08 ,  H01L21/265

Abstract: An ion implantation system including an ion implanter, a dopant source gas supply system and a monitoring system is provided. The ion implanter is inside a housing and includes an ion source unit. The dopant source gas supply system includes a first and a second dopant source gas storage cylinder in a gas cabinet outside of the housing and configured to supply a dopant source gas to the ion source unit, and a first and a second dopant source gas supply pipe coupled to respective first and second dopant source gas storage cylinders. Each of the first and second dopant source gas supply pipes includes an inner pipe and an outer pipe enclosing the inner pipe. The monitoring system is coupled to the outer pipe of each of the first and the second dopant source gas supply pipes.

公开(公告)号：US11355366B2

公开(公告)日：2022-06-07

申请号：US16551352

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsui-Wei Wang ,  Yung-Li Tsai ,  Chui-Ya Peng

IPC: H01L21/02 ,  H01L21/67 ,  B08B15/04

Abstract: In an embodiment, a system includes: a wafer support configured to secure a wafer; a nozzle configured to dispense a liquid or a gas on the wafer when the nozzle is in an active state of dispensing; a shutter configured to catch the liquid from the nozzle when the shutter is in a first position below the nozzle; and a shutter actuator configured to: move the shutter to the first position in response to the nozzle not being in an inactive state; move the shutter to a second position away from the first position in response to the nozzle being in the active state.

公开(公告)号：US11342202B2

公开(公告)日：2022-05-24

申请号：US16539315

申请日：2019-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yu Lee ,  Sen-Yeo Peng ,  Chui-Ya Peng

IPC: H01L21/67 ,  B08B3/04 ,  H01L21/02 ,  H01L21/687 ,  B08B5/00

Abstract: In an embodiment, a method includes: spinning a wafer around an axis of rotation at a center of the wafer; applying a first stream of liquid along a line starting from an initial point on the wafer adjacent to the center of the wafer, through the center of the wafer, and ending at an edge of the wafer; applying a second stream of liquid to an inner third of the line starting at the initial point and ending at a boundary point; applying a third stream of liquid to a middle third of the line starting at the boundary point; applying a fourth stream of liquid to an outer third of the line ending at the edge of the wafer; applying a fifth stream of liquid along the line starting from the initial point and ending at the edge of the wafer; and applying a stream of gas along the line starting from the initial point and ending at the edge of the wafer.