公开(公告)号：US10446669B2

公开(公告)日：2019-10-15

申请号：US15964398

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Fan ,  Wei-Yuan Lu ,  Yu-Lin Yang ,  Chun-Hsiang Fan ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311

Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.

公开(公告)号：US20250056823A1

公开(公告)日：2025-02-13

申请号：US18931886

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US20240047545A1

公开(公告)日：2024-02-08

申请号：US17879638

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Yu Liao ,  Ta-Wei Lin ,  Tsu-Hui Su ,  Chun-Hsiang Fan ,  Chun-Hsiang Fan ,  Kuo-Bin Huang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L21/306 ,  H01L29/66477

Abstract: Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.

公开(公告)号：US20230387263A1

公开(公告)日：2023-11-30

申请号：US18361540

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L22/12

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US11823945B2

公开(公告)日：2023-11-21

申请号：US16876287

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Hua Lin ,  Chun-Liang Tai ,  Chun-Hsiang Fan ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/687 ,  H01L21/67 ,  B08B3/08 ,  B08B3/10

CPC classification number: H01L21/68721 ,  B08B3/08 ,  B08B3/10 ,  H01L21/67051 ,  H01L21/67103 ,  H01L21/68728 ,  H01L21/68735 ,  H01L21/68742

Abstract: A method for cleaning a semiconductor wafer is provided. The method includes placing a semiconductor wafer over a supporter arranged around a central axis of a spin base. The method further includes securing the semiconductor wafer using a clamping member positioned on the supporter. The movement of the semiconductor wafer during the placement of the semiconductor wafer over the supporter is guided by a guiding member located over the clamping member. The method also includes spinning the semiconductor wafer by rotating the spin base about the central axis. In addition, the method includes dispensing a processing liquid over the semiconductor wafer.

公开(公告)号：US20220359734A1

公开(公告)日：2022-11-10

申请号：US17814185

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Yu Liao ,  Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

公开(公告)号：US20200044062A1

公开(公告)日：2020-02-06

申请号：US16600904

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Fan ,  Wei-Yuan Lu ,  Yu-Lin Yang ,  Chun-Hsiang Fan ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L21/306

Abstract: A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.