公开(公告)号：US11450600B2

公开(公告)日：2022-09-20

申请号：US17004768

申请日：2020-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/532 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/768

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20210358842A1

公开(公告)日：2021-11-18

申请号：US17004768

申请日：2020-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L27/12 ,  H01L23/528 ,  H01L23/532 ,  H01L21/84

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US10515947B2

公开(公告)日：2019-12-24

申请号：US16138785

申请日：2018-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/528

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US10304772B2

公开(公告)日：2019-05-28

申请号：US15599687

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Wei-Chih Chen ,  Chii-Ping Chen ,  Wen-Sheh Huang ,  Bi-Ling Lin ,  Sheng-Feng Liu

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/367 ,  H01L29/423

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

公开(公告)号：US10083955B2

公开(公告)日：2018-09-25

申请号：US15663644

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L23/528 ,  H01L27/0207 ,  H01L28/40

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

公开(公告)号：US11837535B2

公开(公告)日：2023-12-05

申请号：US17812887

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L21/768 ,  H01L21/8238 ,  G11C11/22

CPC classification number: H01L23/5223 ,  H01L21/845 ,  H01L23/5286 ,  H01L23/5329 ,  H01L27/1211 ,  G11C11/221 ,  H01L21/7681 ,  H01L21/823821 ,  H01L23/528

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20230386993A1

公开(公告)日：2023-11-30

申请号：US18446648

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528 ,  H01L23/532 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L23/5223 ,  H01L21/845 ,  H01L27/1211 ,  H01L23/5286 ,  H01L23/5329 ,  G11C11/221 ,  H01L21/7681 ,  H01L21/823821 ,  H01L23/528

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US11817452B2

公开(公告)日：2023-11-14

申请号：US17227199

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hui Chen ,  Hao-Chieh Chan ,  Wei-Chih Chen

IPC: H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01L23/528 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/40

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.

公开(公告)号：US20220208957A1

公开(公告)日：2022-06-30

申请号：US17655431

申请日：2022-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/08 ,  H01L27/06 ,  H01L29/94

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US09123556B2

公开(公告)日：2015-09-01

申请号：US14178383

申请日：2014-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hui Chen

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/02

CPC classification number: H01L27/067 ,  H01L21/76224 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/40 ,  H01L28/88 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

Abstract translation: 半导体衬底具有至少两个有源区，每个有源区具有至少一个有源器件，其包括栅极电极层和有源区之间的浅沟槽隔离（STI）区域。 去耦电容器包括在STI区域上形成在同一栅极电极层中的第一和第二虚设导电图案。 第一和第二虚拟导电区域未连接到至少一个有源器件中的任何一个。 第一虚拟导电图案连接到第一电位的源。 第二虚拟导电图案连接到第二电位的源。 介电材料设置在第一和第二虚设导电图案之间。