公开(公告)号：US20240290886A1

公开(公告)日：2024-08-29

申请号：US18654766

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Lien Jung Hung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818

Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

公开(公告)号：US20240260248A1

公开(公告)日：2024-08-01

申请号：US18608045

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes a first transistor and a well strap feature disposed over a doped region of a first type dopant. The first transistor includes a first gate structure engaging a first channel region and a first epitaxial feature abutting the first channel region. The well-strap feature incudes a plurality of first nanostructures vertically stacked, a second gate structure wrapping around each of the first nanostructures, and a second epitaxial feature abutting the first nanostructures. The well-strap feature is configured to bias the doped region by electrically connecting the second epitaxial feature to a bias voltage.

公开(公告)号：US10522553B2

公开(公告)日：2019-12-31

申请号：US16047586

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.

公开(公告)号：US12193205B2

公开(公告)日：2025-01-07

申请号：US18313041

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hung Lo ,  Feng-Ming Chang ,  Ying-Hsiu Kuo

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

Abstract: A static random access memory device is provided and includes a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate and a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of a substrate. A boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.

公开(公告)号：US11942145B2

公开(公告)日：2024-03-26

申请号：US17662364

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Jui-Wen Chang ,  Feng-Ming Chang ,  Kian-Long Lim ,  Kuo-Hsiu Hsu ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: G11C5/06 ,  G11C11/417 ,  H01L29/423 ,  H10B10/00

CPC classification number: G11C11/417 ,  H01L29/42392 ,  H10B10/125

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

公开(公告)号：US20230267263A1

公开(公告)日：2023-08-24

申请号：US18308860

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ming Chang ,  Ruey-Wen Chang ,  Ping-Wei Wang ,  Sheng-Hsiung Wang ,  Chi-Yu Lu

IPC: G06F30/392 ,  H01L27/088 ,  G06F30/398 ,  H10B10/00

CPC classification number: G06F30/392 ,  H01L27/0886 ,  G06F30/398 ,  H10B10/12

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

公开(公告)号：US11690209B2

公开(公告)日：2023-06-27

申请号：US16984983

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC: H10B10/00

CPC classification number: H10B10/12 ,  H10B10/18

Abstract: An integrated circuit device includes a FinFET disposed over a doped region of a first type dopant, wherein the FinFET includes a first fin structure and first source/drain (S/D) features, the first fin structure having a first width; and a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes a second fin structure and second S/D features, the second fin structure having a second width that is larger than the first width, wherein the fin-based well strap connects the doped region to a voltage.

公开(公告)号：US11683924B2

公开(公告)日：2023-06-20

申请号：US17698929

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hung Lo ,  Feng-Ming Chang ,  Ying-Hsiu Kuo

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

Abstract: A static random access memory device includes a first gate of a write port circuit disposed in a standard threshold voltage region of a substrate and a second gate of a read port circuit disposed in a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. A distance between a first edge, corresponding to an edge of the first gate, and a boundary, between the standard threshold voltage region and the low threshold voltage region, is different from a distance between the boundary and a second edge, corresponding to an edge of the second gate.

公开(公告)号：US11682451B2

公开(公告)日：2023-06-20

申请号：US17407005

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yuan Chang ,  Kian-Long Lim ,  Jui-Lin Chen ,  Feng-Ming Chang

IPC: G11C11/419 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/18

Abstract: The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

公开(公告)号：US20230059973A1

公开(公告)日：2023-02-23

申请号：US17982163

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.